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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief Cortex-M3 IRQ management.
35 * \author Andrea Righi <arighi@develer.com>
38 #include <cfg/debug.h> /* ASSERT() */
39 #include <cfg/log.h> /* LOG_ERR() */
43 static void (*irq_table[NUM_INTERRUPTS])(void)
44 __attribute__((section("vtable")));
46 /* Priority register / IRQ number table */
47 static const uint32_t nvic_prio_reg[] =
49 /* System exception registers */
50 0, NVIC_SYS_PRI1, NVIC_SYS_PRI2, NVIC_SYS_PRI3,
52 /* External interrupts registers */
53 NVIC_PRI0, NVIC_PRI1, NVIC_PRI2, NVIC_PRI3,
54 NVIC_PRI4, NVIC_PRI5, NVIC_PRI6, NVIC_PRI7,
55 NVIC_PRI8, NVIC_PRI9, NVIC_PRI10, NVIC_PRI11,
56 NVIC_PRI12, NVIC_PRI13
60 static NAKED NORETURN void unhandled_isr(void)
62 register uint32_t reg;
64 asm volatile ("mrs %0, ipsr" : "=r"(reg));
65 LOG_ERR("unhandled IRQ %lu\n", reg);
70 void sysirq_setPriority(sysirq_t irq, int prio)
72 uint32_t pos = (irq & 3) * 8;
73 reg32_t reg = nvic_prio_reg[irq >> 2];
77 val &= ~(0xff << pos);
82 static void sysirq_enable(sysirq_t irq)
84 /* Enable the IRQ line (only for generic IRQs) */
85 if (irq >= 16 && irq < 48)
86 NVIC_EN0_R = 1 << (irq - 16);
88 NVIC_EN1_R = 1 << (irq - 48);
91 void sysirq_setHandler(sysirq_t irq, sysirq_handler_t handler)
95 ASSERT(irq < NUM_INTERRUPTS);
97 IRQ_SAVE_DISABLE(flags);
98 irq_table[irq] = handler;
99 sysirq_setPriority(irq, IRQ_PRIO);
104 void sysirq_freeHandler(sysirq_t irq)
108 ASSERT(irq < NUM_INTERRUPTS);
110 IRQ_SAVE_DISABLE(flags);
111 irq_table[irq] = unhandled_isr;
115 void sysirq_init(void)
120 IRQ_SAVE_DISABLE(flags);
121 for (i = 0; i < NUM_INTERRUPTS; i++)
122 irq_table[i] = unhandled_isr;
124 /* Update NVIC to point to the new vector table */
125 NVIC_VTABLE_R = (size_t)irq_table;