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14 * GNU General Public License for more details.
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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \brief ADC hardware-specific implementation
35 * This ADC module should be use both whit kernel or none.
36 * If you are using a kernel, the adc drive does not wait the finish of
37 * conversion but use a singal every time a required conversion are
38 * ended. This signal wake up a process that return a result of
39 * conversion. Otherwise, if you not use a kernl, this module wait
40 * whit a loop the finishing of conversion.
43 * \author Daniele Basile <asterix@develer.com>
51 #include "cfg/cfg_adc.h"
52 #include "cfg/cfg_proc.h"
53 #include "cfg/cfg_signal.h"
55 #include <cfg/macros.h>
56 #include <cfg/compiler.h>
57 #include <cfg/debug.h>
59 // Define log settings for cfg/log.h.
60 #define LOG_LEVEL ADC_LOG_LEVEL
61 #define LOG_FORMAT ADC_LOG_FORMAT
65 #include <drv/timer.h>
66 #include <drv/clock_lm3s.h>
70 /* Select witch ADC use */
71 #if CPU_CM3_LM3S1968 || CPU_CM3_LM3S8962
72 #define ADC_BASE ADC0_BASE
73 #define SYSCTL_RCGC_R SYSCTL_RCGC0_R
74 #define SYSCTL_RCGC_ADC SYSCTL_RCGC0_ADC0
76 #error Unknow ADC register for select cpu core
81 #include <cfg/module.h>
83 #include <kern/proc.h>
84 #include <kern/signal.h>
86 #include <drv/irq_cm3.h>
89 #if !CONFIG_KERN_SIGNALS
90 #error Signals must be active to use ADC with kernel
93 /* Signal adc convertion end */
94 #define SIG_ADC_COMPLETE SIG_USER0
96 /* ADC waiting process */
97 static struct Process *adc_process;
101 * Simply signal the adc process that convertion is complete.
103 static DECLARE_ISR(adc_conversion_end_irq)
105 sig_post(adc_process, SIG_ADC_COMPLETE);
107 /* Clear the status bit */
108 HWREG(ADC_BASE + ADC_O_ISC) |= ADC_ISC_IN3;
112 static void adc_enable_irq(void)
114 /* Clear all pending irq */
115 HWREG(ADC_BASE + ADC_O_ISC) = 0;
116 /* Register the IRQ handler */
117 sysirq_setHandler(INT_ADC3, adc_conversion_end_irq);
119 HWREG(ADC_BASE + ADC_O_SSCTL3) |= ADC_SSCTL3_IE0;
120 HWREG(ADC_BASE + ADC_O_IM) |= ADC_IM_MASK3;
123 #endif /* CONFIG_KERN */
126 * Select mux channel \a ch.
127 * Generally the stm32 cpu family allow us to program the order
128 * of adc channel that we want to read.
129 * In this driver implementation we put as fist channel to read the
132 void adc_hw_select_ch(uint8_t ch)
134 /* Select channel that we want read */
135 HWREG(ADC_BASE + ADC_O_SSMUX3) = ch;
136 /* Make single acquisition */
137 HWREG(ADC_BASE + ADC_O_SSCTL3) |= ADC_SSCTL3_END0;
138 /* Enable sequence S03 (single sample on select channel) */
139 HWREG(ADC_BASE + ADC_O_ACTSS) |= ADC_ACTSS_ASEN3;
143 * Start an ADC convertion.
144 * If a kernel is present, preempt until convertion is complete, otherwise
145 * a busy wait on ADC_DRDY bit is done.
147 uint16_t adc_hw_read(void)
150 /* Ensure ADC is not already in use by another process */
151 ASSERT(adc_process == NULL);
152 adc_process = proc_current();
155 /* Start convertion */
156 HWREG(ADC0_BASE + ADC_O_PSSI) |= ADC_PSSI_SS3;
159 /* Ensure IRQs enabled. */
160 IRQ_ASSERT_ENABLED();
161 sig_wait(SIG_ADC_COMPLETE);
163 /* Prevent race condition in case of preemptive kernel */
164 uint16_t ret = (uint16_t)HWREG(ADC_BASE + ADC_O_SSFIFO3);
169 /* Wait in polling until conversion is done */
170 while (!(HWREG(ADC_BASE + ADC_O_SSFSTAT3) & ADC_SSFSTAT3_FULL));
172 /* Return the last converted data */
173 return (uint16_t)HWREG(ADC_BASE + ADC_O_SSFIFO3);
180 void adc_hw_init(void)
182 /* Enable ADC0 clock */
183 SYSCTL_RCGC_R |= SYSCTL_RCGC_ADC;
186 * We wait some time because the clock is istable
187 * and that could cause system hardfault
191 /* Disable all sequence */
192 HWREG(ADC_BASE + ADC_O_ACTSS) = 0;
193 /* Set trigger event to programmed (for all sequence) */
194 HWREG(ADC_BASE + ADC_O_EMUX) = 0;