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29 * Copyright 2008 Develer S.r.l. (http://www.develer.com/)
34 * \brief ADC hardware-specific implementation
36 * This ADC module should be use both whit kernel or none.
37 * If you are using a kernel, the adc drive does not wait the finish of
38 * conversion but use a singal every time a required conversion are
39 * ended. This signal wake up a process that return a result of
40 * conversion. Otherwise, if you not use a kernl, this module wait
41 * whit a loop the finishing of conversion.
46 * \author Daniele Basile <asterix@develer.com>
51 #include "cfg/cfg_adc.h"
52 #include "cfg/cfg_kern.h"
53 #include <cfg/macros.h>
54 #include <cfg/compiler.h>
61 #include <cfg/module.h>
62 #include <kern/proc.h>
63 #include <kern/signal.h>
66 #if !CONFIG_KERN_SIGNALS
67 #error Signals must be active to use ADC with kernel
70 /* Signal adc convertion end */
71 #define SIG_ADC_COMPLETE SIG_USER0
73 /* ADC waiting process */
74 static struct Process *adc_process;
78 * Simply signal the adc process that convertion is complete.
80 static void ISR_FUNC adc_conversion_end_irq(void)
82 sig_signal(adc_process, SIG_ADC_COMPLETE);
84 /* Inform hw that we have served the IRQ */
88 static void adc_enable_irq(void)
91 // Disable all interrupt
94 //Register interrupt vector
95 AIC_SVR(ADC_ID) = adc_conversion_end_irq;
96 AIC_SMR(ADC_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED;
97 AIC_IECR = BV(ADC_ID);
99 //Enable data ready irq
100 ADC_IER = BV(ADC_DRDY);
103 #endif /* CONFIG_KERNEL */
107 * Select mux channel \a ch.
108 * \todo only first 8 channels are selectable!
110 INLINE void adc_hw_select_ch(uint8_t ch)
112 //Disable all channels
113 ADC_CHDR = ADC_CH_MASK;
114 //Enable select channel
120 * Start an ADC convertion.
121 * If a kernel is present, preempt until convertion is complete, otherwise
122 * a busy wait on ADCS bit is done.
124 INLINE uint16_t adc_hw_read(void)
126 ASSERT(!(ADC_SR & ADC_EOC_MASK));
129 adc_process = proc_current();
133 ADC_CR = BV(ADC_START);
136 // Ensure IRQs enabled.
137 ASSERT(IRQ_ENABLED());
138 sig_wait(SIG_ADC_COMPLETE);
140 //Wait in polling until is done
141 while (!(ADC_SR & BV(ADC_DRDY)));
144 //Return the last converted data
151 INLINE void adc_hw_init(void)
157 * Set adc mode register:
158 * - Disable hardware trigger and enable software trigger.
159 * - Select normal mode.
160 * - Set ADC_BITS bit convertion resolution.
166 ADC_MR &= ~BV(ADC_LOWRES);
168 ADC_MR |= BV(ADC_LOWRES);
170 #error No select bit resolution is supported to this CPU
174 TRACEMSG("prescaler[%ld], stup[%ld], shtim[%ld]\n",ADC_COMPUTED_PRESCALER,ADC_COMPUTED_STARTUPTIME,ADC_COMPUTED_SHTIME);
177 //Apply computed prescaler value
178 ADC_MR &= ~ADC_PRESCALER_MASK;
179 ADC_MR |= ((ADC_COMPUTED_PRESCALER << ADC_PRESCALER_SHIFT) & ADC_PRESCALER_MASK);
180 TRACEMSG("prescaler[%ld]\n", (ADC_COMPUTED_PRESCALER << ADC_PRESCALER_SHIFT) & ADC_PRESCALER_MASK);
182 //Apply computed start up time
183 ADC_MR &= ~ADC_STARTUP_MASK;
184 ADC_MR |= ((ADC_COMPUTED_STARTUPTIME << ADC_STARTUP_SHIFT) & ADC_STARTUP_MASK);
185 TRACEMSG("sttime[%ld]\n", (ADC_COMPUTED_STARTUPTIME << ADC_STARTUP_SHIFT) & ADC_STARTUP_MASK);
187 //Apply computed sample and hold time
188 ADC_MR &= ~ADC_SHTIME_MASK;
189 ADC_MR |= ((ADC_COMPUTED_SHTIME << ADC_SHTIME_SHIFT) & ADC_SHTIME_MASK);
190 TRACEMSG("shtime[%ld]\n", (ADC_COMPUTED_SHTIME << ADC_SHTIME_SHIFT) & ADC_SHTIME_MASK);
193 //Register and enable irq for adc.