4 * This file is part of BeRTOS.
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7 * it under the terms of the GNU General Public License as published by
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
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24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2008 Develer S.r.l. (http://www.develer.com/)
34 * \brief PWM hardware-specific implementation
38 * \author Daniele Basile <asterix@develer.com>
42 #include "hw/pwm_map.h"
43 #include "hw/hw_cpu.h"
45 #include <cfg/macros.h>
46 #include <cfg/debug.h>
52 * Register structure for pwm driver.
53 * This array content all data and register pointer
54 * to manage pwm peripheral device.
56 static PwmChannel pwm_map[PWM_CNT] =
62 .mode_reg = &PWM_CMR0,
63 .duty_reg = &PWM_CDTY0,
64 .period_reg = &PWM_CPRD0,
65 .update_reg = &PWM_CUPD0,
71 .mode_reg = &PWM_CMR1,
72 .duty_reg = &PWM_CDTY1,
73 .period_reg = &PWM_CPRD1,
74 .update_reg = &PWM_CUPD1,
80 .mode_reg = &PWM_CMR2,
81 .duty_reg = &PWM_CDTY2,
82 .period_reg = &PWM_CPRD2,
83 .update_reg = &PWM_CUPD2,
89 .mode_reg = &PWM_CMR3,
90 .duty_reg = &PWM_CDTY3,
91 .period_reg = &PWM_CPRD3,
92 .update_reg = &PWM_CUPD3,
98 * Get preiod from select channel
102 pwm_period_t pwm_hw_getPeriod(PwmDev dev)
104 return *pwm_map[dev].period_reg;
108 * Set pwm waveform frequecy.
112 void pwm_hw_setFrequency(PwmDev dev, uint32_t freq)
116 for(int i = 0; i <= PWM_HW_MAX_PRESCALER_STEP; i++)
118 period = CLOCK_FREQ / (BV(i) * freq);
119 // TRACEMSG("period[%ld], prescale[%d]", period, i);
120 if ((period < PWM_HW_MAX_PERIOD) && (period != 0))
122 //Clean previous channel prescaler, and set new
123 *pwm_map[dev].mode_reg &= ~PWM_CPRE_MCK_MASK;
124 *pwm_map[dev].mode_reg |= i;
126 *pwm_map[dev].period_reg = period;
131 TRACEMSG("PWM ch[%d] period[%ld]", dev, period);
135 * Set pwm duty cycle.
137 * \a duty value 0 - 2^16
139 void pwm_hw_setDutyUnlock(PwmDev dev, uint16_t duty)
141 ASSERT(duty <= (uint16_t)*pwm_map[dev].period_reg);
145 * WARNING: is forbidden to write 0 to duty cycle value,
146 * and so for duty = 0 we must enable PIO and clear output!
150 PWM_PIO_PER = pwm_map[dev].pwm_pin;
151 pwm_map[dev].duty_zero = true;
157 * If polarity flag is true we must invert
160 if (pwm_map[dev].pol)
162 duty = (uint16_t)*pwm_map[dev].period_reg - duty;
163 // TRACEMSG("Inverted duty[%d], pol[%d]", duty, pwm_map[dev].pol);
166 PWM_PIO_PDR = pwm_map[dev].pwm_pin;
167 *pwm_map[dev].update_reg = duty;
168 pwm_map[dev].duty_zero = false;
173 // TRACEMSG("PWM ch[%d] duty[%d], period[%ld]", dev, duty, *pwm_map[dev].period_reg);
178 * Enable select pwm channel
180 void pwm_hw_enable(PwmDev dev)
182 if (!pwm_map[dev].duty_zero)
183 PWM_PIO_PDR = pwm_map[dev].pwm_pin;
187 * Disable select pwm channel
189 void pwm_hw_disable(PwmDev dev)
191 PWM_PIO_PER = pwm_map[dev].pwm_pin;
195 * Set PWM polarity to select pwm channel
197 void pwm_hw_setPolarity(PwmDev dev, bool pol)
199 pwm_map[dev].pol = pol;
200 // TRACEMSG("Set pol[%d]", pwm_map[dev].pol);
206 void pwm_hw_init(void)
211 * WARNING: is forbidden to write 0 to duty cycle value,
212 * and so for duty = 0 we must enable PIO and clear output!
213 * - clear PIO outputs
214 * - enable PIO outputs
215 * - Disable PIO and enable PWM functions
218 PWM_PIO_CODR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
219 PWM_PIO_OER = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
220 PWM_PIO_PDR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
221 PWM_PIO_ABSR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
222 PMC_PCER |= BV(PWMC_ID);
224 /* Disable all channels. */
225 PWM_DIS = 0xFFFFFFFF;
226 /* Disable prescalers A and B */
231 * - set period alidned to left
232 * - set output waveform to start at high level
233 * - allow duty cycle modify at next period event
235 for (int ch = 0; ch < PWM_CNT; ch++)
237 *pwm_map[ch].mode_reg = 0;
238 *pwm_map[ch].mode_reg = BV(PWM_CPOL);