4 * This file is part of BeRTOS.
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
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26 * invalidate any other reasons why the executable file might be covered by
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29 * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
32 * \brief ADC hardware-specific definition
34 * \author Francesco Sacchi <batt@develer.com>
36 * This module is automatically included so no need to include
45 #include "cfg/cfg_adc.h"
46 #include "cfg/cfg_proc.h"
47 #include "cfg/cfg_signal.h"
48 #include <cfg/macros.h>
49 #include <cfg/compiler.h>
51 #include <cpu/irq.h> // IRQ_ASSERT_ENABLED()
56 #include <avr/interrupt.h>
59 * ADC voltage referencese.
61 * $WIZ$ avr_adc_refs = "ADC_AVR_AREF", "ADC_AVR_AVCC", "ADC_AVR_INT256"
64 #define ADC_AVR_AREF 0
65 #define ADC_AVR_AVCC 1
66 #define ADC_AVR_INT256 2
70 #include <cfg/module.h>
71 #include <kern/proc.h>
72 #include <kern/signal.h>
75 #if !CONFIG_KERN_SIGNALS
76 #error Signals must be active to use the ADC with kernel
79 /* Signal adc convertion end */
80 #define SIG_ADC_COMPLETE SIG_SINGLE
82 /* ADC waiting process */
83 static struct Process *adc_process;
87 * Simply signal the adc process that convertion is complete.
91 sig_post(adc_process, SIG_ADC_COMPLETE);
93 #endif /* CONFIG_KERN */
96 * Select mux channel \a ch.
97 * \todo only first 8 channels are selectable!
99 void adc_hw_select_ch(uint8_t ch)
101 /* Set to 0 all mux registers */
102 #if CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA168
103 ADMUX &= ~(BV(MUX3) | BV(MUX2) | BV(MUX1) | BV(MUX0));
104 #elif CPU_AVR_ATMEGA32 || CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
105 ADMUX &= ~(BV(MUX4) | BV(MUX3) | BV(MUX2) | BV(MUX1) | BV(MUX0));
110 /* Select channel, only first 8 channel modes are supported for now */
111 ADMUX |= (ch & 0x07);
116 * Start an ADC convertion.
117 * If a kernel is present, preempt until convertion is complete, otherwise
118 * a busy wait on ADCS bit is done.
120 uint16_t adc_hw_read(void)
122 // Ensure another convertion is not running.
123 ASSERT(!(ADCSRA & BV(ADSC)));
129 // Ensure IRQs enabled.
130 IRQ_ASSERT_ENABLED();
131 adc_process = proc_current();
132 sig_wait(SIG_ADC_COMPLETE);
134 //Wait in polling until is done
135 while (ADCSRA & BV(ADSC)) ;
144 void adc_hw_init(void)
147 * Select channel 0 as default,
148 * result right adjusted.
152 #if CONFIG_ADC_AVR_REF == ADC_AVR_AREF
153 /* External voltage at AREF as analog ref source */
155 #elif CONFIG_ADC_AVR_REF == ADC_AVR_AVCC
156 /* AVCC as analog ref source */
158 #elif CONFIG_ADC_AVR_REF == ADC_AVR_INT256
159 /* Internal 2.56V as ref source */
160 ADMUX |= BV(REFS1) | BV(REFS0);
162 #error Unsupported ADC ref value.
166 /* Disable Auto trigger source: ADC in Free running mode. */
170 /* Enable ADC, disable autotrigger mode. */
178 /* Set convertion frequency */
179 #if CONFIG_ADC_AVR_DIVISOR == 2
181 #elif CONFIG_ADC_AVR_DIVISOR == 4
183 #elif CONFIG_ADC_AVR_DIVISOR == 8
184 ADCSRA |= BV(ADPS1) | BV(ADPS0);
185 #elif CONFIG_ADC_AVR_DIVISOR == 16
187 #elif CONFIG_ADC_AVR_DIVISOR == 32
188 ADCSRA |= BV(ADPS2) | BV(ADPS0);
189 #elif CONFIG_ADC_AVR_DIVISOR == 64
190 ADCSRA |= BV(ADPS2) | BV(ADPS1);
191 #elif CONFIG_ADC_AVR_DIVISOR == 128
192 ADCSRA |= BV(ADPS2) | BV(ADPS1) | BV(ADPS0);
194 #error Unsupported ADC prescaler value.
197 /* Start a convertion to init ADC hw */