4 * This file is part of BeRTOS.
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14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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21 * library without restriction. Specifically, if other files instantiate
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27 * the GNU General Public License.
29 * Copyright 2008 Develer S.r.l. (http://www.develer.com/)
33 * \brief ADC hardware-specific implementation
35 * This ADC module should be use both whit kernel or none.
36 * If you are using a kernel, the adc drive does not wait the finish of
37 * conversion but use a singal every time a required conversion are
38 * ended. This signal wake up a process that return a result of
39 * conversion. Otherwise, if you not use a kernl, this module wait
40 * whit a loop the finishing of conversion.
43 * \author Daniele Basile <asterix@develer.com>
51 #include "cfg/cfg_adc.h"
52 #include "cfg/cfg_proc.h"
53 #include "cfg/cfg_signal.h"
54 #include <cfg/macros.h>
55 #include <cfg/compiler.h>
57 // Define log settings for cfg/log.h.
58 #define LOG_LEVEL ADC_LOG_LEVEL
59 #define LOG_FORMAT ADC_LOG_FORMAT
67 #include <cfg/module.h>
68 #include <kern/proc.h>
69 #include <kern/signal.h>
72 #if !CONFIG_KERN_SIGNALS
73 #error Signals must be active to use ADC with kernel
76 /* Signal adc convertion end */
77 #define SIG_ADC_COMPLETE SIG_USER0
79 /* ADC waiting process */
80 static struct Process *adc_process;
84 * Simply signal the adc process that convertion is complete.
86 static DECLARE_ISR(adc_conversion_end_irq)
88 sig_post(adc_process, SIG_ADC_COMPLETE);
90 /* Inform hw that we have served the IRQ */
94 static void adc_enable_irq(void)
97 // Disable all interrupt
100 //Register interrupt vector
101 AIC_SVR(ADC_ID) = adc_conversion_end_irq;
102 AIC_SMR(ADC_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED;
103 AIC_IECR = BV(ADC_ID);
105 //Enable data ready irq
106 ADC_IER = BV(ADC_DRDY);
109 #endif /* CONFIG_KERN */
113 * Select mux channel \a ch.
114 * \todo only first 8 channels are selectable!
116 void adc_hw_select_ch(uint8_t ch)
118 //Disable all channels
119 ADC_CHDR = ADC_CH_MASK;
120 //Enable select channel
126 * Start an ADC convertion.
127 * If a kernel is present, preempt until convertion is complete, otherwise
128 * a busy wait on ADC_DRDY bit is done.
130 uint16_t adc_hw_read(void)
133 /* Ensure ADC is not already in use by another process */
134 ASSERT(adc_process == NULL);
135 adc_process = proc_current();
139 ADC_CR = BV(ADC_START);
142 // Ensure IRQs enabled.
143 IRQ_ASSERT_ENABLED();
144 sig_wait(SIG_ADC_COMPLETE);
146 /* Prevent race condition in case of preemptive kernel */
147 uint16_t ret = ADC_LCDR;
152 //Wait in polling until is done
153 while (!(ADC_SR & BV(ADC_DRDY)));
155 //Return the last converted data
163 void adc_hw_init(void)
169 * Set adc mode register:
170 * - Disable hardware trigger and enable software trigger.
171 * - Select normal mode.
172 * - Set ADC_BITS bit convertion resolution.
178 ADC_MR &= ~BV(ADC_LOWRES);
180 ADC_MR |= BV(ADC_LOWRES);
182 #error No select bit resolution is supported to this CPU
186 LOG_INFO("Computed ADC_CLOCK %ld\n", ADC_COMPUTED_CLOCK);
187 LOG_INFO("prescaler[%ld], stup[%ld], shtim[%ld]\n",ADC_COMPUTED_PRESCALER, ADC_COMPUTED_STARTUPTIME, ADC_COMPUTED_SHTIME);
190 //Apply computed prescaler value
191 ADC_MR &= ~ADC_PRESCALER_MASK;
192 ADC_MR |= ((ADC_COMPUTED_PRESCALER << ADC_PRESCALER_SHIFT) & ADC_PRESCALER_MASK);
193 LOG_INFO("prescaler[%ld]\n", (ADC_COMPUTED_PRESCALER << ADC_PRESCALER_SHIFT) & ADC_PRESCALER_MASK);
195 //Apply computed start up time
196 ADC_MR &= ~ADC_STARTUP_MASK;
197 ADC_MR |= ((ADC_COMPUTED_STARTUPTIME << ADC_STARTUP_SHIFT) & ADC_STARTUP_MASK);
198 LOG_INFO("sttime[%ld]\n", (ADC_COMPUTED_STARTUPTIME << ADC_STARTUP_SHIFT) & ADC_STARTUP_MASK);
200 //Apply computed sample and hold time
201 ADC_MR &= ~ADC_SHTIME_MASK;
202 ADC_MR |= ((ADC_COMPUTED_SHTIME << ADC_SHTIME_SHIFT) & ADC_SHTIME_MASK);
203 LOG_INFO("shtime[%ld]\n", (ADC_COMPUTED_SHTIME << ADC_SHTIME_SHIFT) & ADC_SHTIME_MASK);
206 //Register and enable irq for adc.