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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
30 * All Rights Reserved.
33 * \brief EMAC driver for AT91SAM7X Family.
35 * \author Daniele Basile <asterix@develer.com>
36 * \author Andrea Righi <arighi@develer.com>
39 #include "cfg/cfg_eth.h"
41 #define LOG_LEVEL ETH_LOG_LEVEL
42 #define LOG_FORMAT ETH_LOG_FORMAT
46 #include <cfg/debug.h>
48 #include <cfg/macros.h>
49 #include <cfg/compiler.h>
51 #include <io/at91sam7.h>
54 #include <cpu/power.h>
55 #include <cpu/types.h>
58 #include <drv/timer.h>
61 #include <mware/event.h>
67 #define EMAC_RX_INTS (BV(EMAC_RCOMP) | BV(EMAC_ROVR) | BV(EMAC_RXUBR))
68 #define EMAC_TX_INTS (BV(EMAC_TCOMP) | BV(EMAC_TXUBR) | BV(EMAC_RLEX))
71 * MAC address configuration (please change this in your project!).
73 * TODO: make this paramater user-configurable from the Wizard.
75 const uint8_t mac_addr[] = { 0x00, 0x11, 0x22, 0x33, 0x44, 0x55 };
77 /* Silent Doxygen bug... */
80 * NOTE: this buffer should be declared as 'volatile' because it is read by the
81 * hardware. However, this is accessed only via memcpy() that should guarantee
82 * coherency when copying from/to buffers.
84 static uint8_t tx_buf[EMAC_TX_BUFFERS * EMAC_TX_BUFSIZ] ALIGNED(8);
85 static volatile BufDescriptor tx_buf_tab[EMAC_TX_DESCRIPTORS] ALIGNED(8);
88 * NOTE: this buffer should be declared as 'volatile' because it is wrote by
89 * the hardware. However, this is accessed only via memcpy() that should
90 * guarantee coherency when copying from/to buffers.
92 static uint8_t rx_buf[EMAC_RX_BUFFERS * EMAC_RX_BUFSIZ] ALIGNED(8);
93 static volatile BufDescriptor rx_buf_tab[EMAC_RX_DESCRIPTORS] ALIGNED(8);
96 static int tx_buf_idx;
97 static int tx_buf_offset;
98 static int rx_buf_idx;
100 static Event recv_wait, send_wait;
102 static DECLARE_ISR(emac_irqHandler)
104 /* Read interrupt status and disable interrupts. */
105 uint32_t isr = EMAC_ISR;
107 /* Receiver interrupt */
108 if ((isr & EMAC_RX_INTS))
110 if (isr & BV(EMAC_RCOMP))
111 event_do(&recv_wait);
112 EMAC_RSR = EMAC_RX_INTS;
114 /* Transmitter interrupt */
115 if (isr & EMAC_TX_INTS)
117 if (isr & BV(EMAC_TCOMP))
118 event_do(&send_wait);
119 EMAC_TSR = EMAC_TX_INTS;
125 * \brief Read contents of PHY register.
127 * \param reg PHY register number.
129 * \return Contents of the specified register.
131 static uint16_t phy_hw_read(reg8_t reg)
134 EMAC_MAN = EMAC_SOF | EMAC_RW_READ | (NIC_PHY_ADDR << EMAC_PHYA_SHIFT)
135 | ((reg << EMAC_REGA_SHIFT) & EMAC_REGA) | EMAC_CODE;
137 // Wait until PHY logic completed.
138 while (!(EMAC_NSR & BV(EMAC_IDLE)))
141 // Get data from PHY maintenance register.
142 return (uint16_t)(EMAC_MAN & EMAC_DATA);
146 * \brief Write value to PHY register.
148 * \param reg PHY register number.
149 * \param val Value to write.
151 static void phy_hw_write(reg8_t reg, uint16_t val)
153 // PHY write command.
154 EMAC_MAN = EMAC_SOF | EMAC_RW_WRITE | (NIC_PHY_ADDR << EMAC_PHYA_SHIFT)
155 | ((reg << EMAC_REGA_SHIFT) & EMAC_REGA) | EMAC_CODE | val;
157 // Wait until PHY logic completed.
158 while (!(EMAC_NSR & BV(EMAC_IDLE)))
162 static int emac_reset(void)
167 PMC_PCER = BV(PIOA_ID);
168 PMC_PCER = BV(PIOB_ID);
169 PMC_PCER = BV(EMAC_ID);
171 // Disable RMII and TESTMODE by disabling pull-ups.
172 PIOB_PUDR = BV(PHY_COL_RMII_BIT) | BV(PHY_RXDV_TESTMODE_BIT);
174 // Disable PHY power down.
175 PIOB_PER = BV(PHY_PWRDN_BIT);
176 PIOB_OER = BV(PHY_PWRDN_BIT);
177 PIOB_CODR = BV(PHY_PWRDN_BIT);
179 // Toggle external hardware reset pin.
180 RSTC_MR = RSTC_KEY | (1 << RSTC_ERSTL_SHIFT) | BV(RSTC_URSTEN);
181 RSTC_CR = RSTC_KEY | BV(RSTC_EXTRST);
183 while ((RSTC_SR & BV(RSTC_NRSTL)) == 0)
186 // Configure MII port.
187 PIOB_ASR = PHY_MII_PINS;
189 PIOB_PDR = PHY_MII_PINS;
191 // Enable receive and transmit clocks.
192 EMAC_USRIO = BV(EMAC_CLKEN);
194 // Enable management port.
195 EMAC_NCR |= BV(EMAC_MPE);
196 EMAC_NCFGR |= EMAC_CLK_HCLK_32;
198 // Set local MAC address.
199 EMAC_SA1L = (mac_addr[3] << 24) | (mac_addr[2] << 16) |
200 (mac_addr[1] << 8) | mac_addr[0];
201 EMAC_SA1H = (mac_addr[5] << 8) | mac_addr[4];
203 // Wait for PHY ready
206 // Clear MII isolate.
207 phy_hw_read(NIC_PHY_BMCR);
208 phy_cr = phy_hw_read(NIC_PHY_BMCR);
210 phy_cr &= ~NIC_PHY_BMCR_ISOLATE;
211 phy_hw_write(NIC_PHY_BMCR, phy_cr);
213 phy_cr = phy_hw_read(NIC_PHY_BMCR);
215 LOG_INFO("%s: PHY ID %#04x %#04x\n",
217 phy_hw_read(NIC_PHY_ID1), phy_hw_read(NIC_PHY_ID2));
219 // Wait for auto negotiation completed.
220 phy_hw_read(NIC_PHY_BMSR);
223 if (phy_hw_read(NIC_PHY_BMSR) & NIC_PHY_BMSR_ANCOMPL)
228 // Disable management port.
229 EMAC_NCR &= ~BV(EMAC_MPE);
234 static int emac_start(void)
239 for (i = 0; i < EMAC_RX_DESCRIPTORS; i++)
241 addr = (uint32_t)(rx_buf + (i * EMAC_RX_BUFSIZ));
242 rx_buf_tab[i].addr = addr & BUF_ADDRMASK;
244 rx_buf_tab[EMAC_RX_DESCRIPTORS - 1].addr |= RXBUF_WRAP;
246 for (i = 0; i < EMAC_TX_DESCRIPTORS; i++)
248 addr = (uint32_t)(tx_buf + (i * EMAC_TX_BUFSIZ));
249 tx_buf_tab[i].addr = addr & BUF_ADDRMASK;
250 tx_buf_tab[i].stat = TXS_USED;
252 tx_buf_tab[EMAC_TX_DESCRIPTORS - 1].stat = TXS_USED | TXS_WRAP;
254 /* Tell the EMAC where to find the descriptors. */
255 EMAC_RBQP = (uint32_t)rx_buf_tab;
256 EMAC_TBQP = (uint32_t)tx_buf_tab;
258 /* Clear receiver status. */
259 EMAC_RSR = BV(EMAC_OVR) | BV(EMAC_REC) | BV(EMAC_BNA);
261 /* Copy all frames and discard FCS. */
262 EMAC_NCFGR |= BV(EMAC_CAF) | BV(EMAC_DRFCS);
264 /* Enable receiver, transmitter and statistics. */
265 EMAC_NCR |= BV(EMAC_TE) | BV(EMAC_RE) | BV(EMAC_WESTAT);
270 ssize_t eth_putFrame(const uint8_t *buf, size_t len)
276 ASSERT(len <= sizeof(tx_buf));
278 /* Check if the transmit buffer is available */
279 while (!(tx_buf_tab[tx_buf_idx].stat & TXS_USED))
280 event_wait(&send_wait);
282 /* Copy the data into the buffer and prepare descriptor */
283 wr_len = MIN(len, (size_t)EMAC_TX_BUFSIZ - tx_buf_offset);
284 memcpy((uint8_t *)tx_buf_tab[tx_buf_idx].addr + tx_buf_offset,
286 tx_buf_offset += wr_len;
291 void eth_sendFrame(void)
293 tx_buf_tab[tx_buf_idx].stat = (tx_buf_offset & TXS_LENGTH_FRAME) |
295 ((tx_buf_idx == EMAC_TX_DESCRIPTORS - 1) ? TXS_WRAP : 0);
296 EMAC_NCR |= BV(EMAC_TSTART);
299 if (++tx_buf_idx >= EMAC_TX_DESCRIPTORS)
303 ssize_t eth_send(const uint8_t *buf, size_t len)
308 len = eth_putFrame(buf, len);
314 static void eth_buf_realign(int idx)
316 /* Empty buffer found. Realign. */
318 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
319 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
321 } while (idx != rx_buf_idx);
324 static size_t __eth_getFrameLen(void)
326 int idx, n = EMAC_RX_BUFFERS;
329 /* Skip empty buffers */
330 while ((n > 0) && !(rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP))
332 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
338 LOG_INFO("no frame found\n");
341 /* Search the start of frame and cleanup fragments */
342 while ((n > 0) && (rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP) &&
343 !(rx_buf_tab[rx_buf_idx].stat & RXS_SOF))
345 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
346 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
352 LOG_INFO("no SOF found\n");
355 /* Search end of frame to evaluate the total frame size */
360 if (UNLIKELY(!(rx_buf_tab[idx].addr & RXBUF_OWNERSHIP)))
362 /* Empty buffer found. Realign. */
363 eth_buf_realign(idx);
366 if (rx_buf_tab[idx].stat & RXS_EOF)
367 return rx_buf_tab[idx].stat & RXS_LENGTH_FRAME;
368 if (UNLIKELY((idx != rx_buf_idx) &&
369 (rx_buf_tab[idx].stat & RXS_SOF)))
371 /* Another start of frame found. Realign. */
372 eth_buf_realign(idx);
375 if (++idx >= EMAC_RX_BUFFERS)
379 LOG_INFO("no EOF found\n");
383 size_t eth_getFrameLen(void)
387 /* Check if there is at least one available frame in the buffer */
390 len = __eth_getFrameLen();
393 /* Wait for RX interrupt */
394 event_wait(&recv_wait);
399 ssize_t eth_getFrame(uint8_t *buf, size_t len)
406 ASSERT(len <= sizeof(rx_buf));
408 /* Copy data from the RX buffer */
409 addr = (uint8_t *)(rx_buf_tab[rx_buf_idx].addr & BUF_ADDRMASK);
410 if (addr + len > &rx_buf[countof(rx_buf)])
412 size_t count = &rx_buf[countof(rx_buf)] - addr;
414 memcpy(buf, addr, count);
415 memcpy(buf + count, rx_buf, len - count);
419 memcpy(buf, addr, len);
421 /* Update descriptors */
424 if (len - rd_len >= EMAC_RX_BUFSIZ)
425 rd_len += EMAC_RX_BUFSIZ;
427 rd_len += len - rd_len;
428 if (UNLIKELY(!(rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP)))
430 LOG_INFO("bad frame found\n");
433 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
434 if (++rx_buf_idx >= EMAC_RX_DESCRIPTORS)
441 ssize_t eth_recv(uint8_t *buf, size_t len)
445 len = MIN(len, eth_getFrameLen());
446 return len ? eth_getFrame(buf, len) : 0;
456 event_initGeneric(&recv_wait);
457 event_initGeneric(&send_wait);
459 // Register interrupt vector
460 IRQ_SAVE_DISABLE(flags);
462 /* Disable all emac interrupts */
463 EMAC_IDR = 0xFFFFFFFF;
465 /* Set the vector. */
466 AIC_SVR(EMAC_ID) = emac_irqHandler;
467 /* Initialize to edge triggered with defined priority. */
468 AIC_SMR(EMAC_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED;
469 /* Clear pending interrupt */
470 AIC_ICCR = BV(EMAC_ID);
471 /* Enable the system IRQ */
472 AIC_IECR = BV(EMAC_ID);
474 /* Enable interrupts */
475 EMAC_IER = EMAC_RX_INTS | EMAC_TX_INTS;