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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
30 * All Rights Reserved.
33 * \brief EMAC driver for AT91SAM7X Family.
35 * \author Daniele Basile <asterix@develer.com>
36 * \author Andrea Righi <arighi@develer.com>
39 #include "cfg/cfg_eth.h"
41 #define LOG_LEVEL ETH_LOG_LEVEL
42 #define LOG_FORMAT ETH_LOG_FORMAT
46 #include <cfg/debug.h>
48 #include <cfg/macros.h>
49 #include <cfg/compiler.h>
51 #include <io/at91sam7.h>
54 #include <cpu/power.h>
55 #include <cpu/types.h>
58 #include <drv/timer.h>
61 #include <mware/event.h>
67 #define EMAC_RX_INTS (BV(EMAC_RCOMP) | BV(EMAC_ROVR) | BV(EMAC_RXUBR))
68 #define EMAC_TX_INTS (BV(EMAC_TCOMP) | BV(EMAC_TXUBR) | BV(EMAC_RLEX))
70 /* Silent Doxygen bug... */
73 * NOTE: this buffer should be declared as 'volatile' because it is read by the
74 * hardware. However, this is accessed only via memcpy() that should guarantee
75 * coherency when copying from/to buffers.
77 static uint8_t tx_buf[EMAC_TX_BUFFERS * EMAC_TX_BUFSIZ] ALIGNED(8);
78 static volatile BufDescriptor tx_buf_tab[EMAC_TX_DESCRIPTORS] ALIGNED(8);
81 * NOTE: this buffer should be declared as 'volatile' because it is wrote by
82 * the hardware. However, this is accessed only via memcpy() that should
83 * guarantee coherency when copying from/to buffers.
85 static uint8_t rx_buf[EMAC_RX_BUFFERS * EMAC_RX_BUFSIZ] ALIGNED(8);
86 static volatile BufDescriptor rx_buf_tab[EMAC_RX_DESCRIPTORS] ALIGNED(8);
89 static int tx_buf_idx;
90 static int tx_buf_offset;
91 static int rx_buf_idx;
93 static Event recv_wait, send_wait;
95 static DECLARE_ISR(emac_irqHandler)
97 /* Read interrupt status and disable interrupts. */
98 uint32_t isr = EMAC_ISR;
100 /* Receiver interrupt */
101 if ((isr & EMAC_RX_INTS))
103 if (isr & BV(EMAC_RCOMP))
104 event_do(&recv_wait);
105 EMAC_RSR = EMAC_RX_INTS;
107 /* Transmitter interrupt */
108 if (isr & EMAC_TX_INTS)
110 if (isr & BV(EMAC_TCOMP))
111 event_do(&send_wait);
112 EMAC_TSR = EMAC_TX_INTS;
118 * \brief Read contents of PHY register.
120 * \param reg PHY register number.
122 * \return Contents of the specified register.
124 static uint16_t phy_hw_read(uint8_t reg)
127 EMAC_MAN = EMAC_SOF | EMAC_RW_READ | (NIC_PHY_ADDR << EMAC_PHYA_SHIFT)
128 | ((reg << EMAC_REGA_SHIFT) & EMAC_REGA) | EMAC_CODE;
130 // Wait until PHY logic completed.
131 while (!(EMAC_NSR & BV(EMAC_IDLE)))
134 // Get data from PHY maintenance register.
135 return (uint16_t)(EMAC_MAN & EMAC_DATA);
139 * \brief Write value to PHY register.
141 * \param reg PHY register number.
142 * \param val Value to write.
144 static void phy_hw_write(uint8_t reg, uint16_t val)
146 // PHY write command.
147 EMAC_MAN = EMAC_SOF | EMAC_RW_WRITE | (NIC_PHY_ADDR << EMAC_PHYA_SHIFT)
148 | ((reg << EMAC_REGA_SHIFT) & EMAC_REGA) | EMAC_CODE | val;
150 // Wait until PHY logic completed.
151 while (!(EMAC_NSR & BV(EMAC_IDLE)))
155 INLINE void phy_manageEnable(bool en)
159 /* Enable management port. */
160 EMAC_NCR |= BV(EMAC_MPE);
161 EMAC_NCFGR |= EMAC_CLK_HCLK_32;
165 /* Disable management port */
166 EMAC_NCR &= ~BV(EMAC_MPE);
170 INLINE void phy_resetPulse(void)
172 /* Toggle external hardware reset pin. */
173 RSTC_MR = RSTC_KEY | (1 << RSTC_ERSTL_SHIFT) | BV(RSTC_URSTEN);
174 RSTC_CR = RSTC_KEY | BV(RSTC_EXTRST);
176 while ((RSTC_SR & BV(RSTC_NRSTL)) == 0)
180 INLINE void phy_pinThreeState(void)
182 PIOB_PUDR = PHY_MII_PINS;
183 PIOB_ODR = PHY_MII_PINS;
184 PIOB_PER = PHY_MII_PINS;
187 INLINE void phy_pinGpio(void)
189 PIOB_PUDR = PHY_MII_PINS;
190 PIOB_OWER = PHY_MII_PINS;
191 PIOB_OER = PHY_MII_PINS;
192 PIOB_PER = PHY_MII_PINS;
195 INLINE void phy_pinMac(void)
197 PIOB_ODR = PHY_MII_PINS;
198 PIOB_OWDR = PHY_MII_PINS;
199 PIOB_ASR = PHY_MII_PINS;
201 PIOB_PUDR = PHY_MII_PINS;
202 PIOB_PDR = PHY_MII_PINS;
205 INLINE void phy_pinSet(uint32_t state)
210 #define AUTONEGOTIATION_TIMEOUT 5000
212 static void emac_reset(void)
215 PMC_PCER = BV(EMAC_ID);
217 /* Enable receive and transmit clocks. */
218 EMAC_USRIO = BV(EMAC_CLKEN);
220 /* Set local MAC address. */
221 EMAC_SA1L = (mac_addr[3] << 24) | (mac_addr[2] << 16) |
222 (mac_addr[1] << 8) | mac_addr[0];
223 EMAC_SA1H = (mac_addr[5] << 8) | mac_addr[4];
224 phy_manageEnable(true);
231 /* Clear MII isolate. */
232 uint16_t phy_cr = phy_hw_read(NIC_PHY_BMCR);
234 phy_cr &= ~NIC_PHY_BMCR_ISOLATE;
235 phy_hw_write(NIC_PHY_BMCR, phy_cr);
237 uint32_t phy_id = phy_hw_read(NIC_PHY_ID1) << 16
238 | phy_hw_read(NIC_PHY_ID2);
239 ASSERT((phy_id & 0xFFFFFFF0) == (NIC_PHY_ID & 0xFFFFFFF0));
240 LOG_INFO("PHY ID %#08lx\n", phy_id);
242 ticks_t start = timer_clock();
243 /* Wait for auto negotiation completed. */
246 if (phy_hw_read(NIC_PHY_BMSR) & NIC_PHY_BMSR_ANCOMPL)
249 if (timer_clock() - start > ms_to_ticks(AUTONEGOTIATION_TIMEOUT))
251 LOG_ERR("Autonegotiation timeout\n");
257 static void emac_start(void)
262 for (i = 0; i < EMAC_RX_DESCRIPTORS; i++)
264 addr = (uint32_t)(rx_buf + (i * EMAC_RX_BUFSIZ));
265 rx_buf_tab[i].addr = addr & BUF_ADDRMASK;
267 rx_buf_tab[EMAC_RX_DESCRIPTORS - 1].addr |= RXBUF_WRAP;
269 for (i = 0; i < EMAC_TX_DESCRIPTORS; i++)
271 addr = (uint32_t)(tx_buf + (i * EMAC_TX_BUFSIZ));
272 tx_buf_tab[i].addr = addr & BUF_ADDRMASK;
273 tx_buf_tab[i].stat = TXS_USED;
275 tx_buf_tab[EMAC_TX_DESCRIPTORS - 1].stat = TXS_USED | TXS_WRAP;
277 /* Tell the EMAC where to find the descriptors. */
278 EMAC_RBQP = (uint32_t)rx_buf_tab;
279 EMAC_TBQP = (uint32_t)tx_buf_tab;
281 /* Clear receiver status. */
282 EMAC_RSR = BV(EMAC_OVR) | BV(EMAC_REC) | BV(EMAC_BNA);
284 /* Copy all frames and discard FCS. */
285 EMAC_NCFGR |= BV(EMAC_CAF) | BV(EMAC_DRFCS);
287 /* Enable receiver, transmitter and statistics. */
288 EMAC_NCR |= BV(EMAC_TE) | BV(EMAC_RE) | BV(EMAC_WESTAT);
291 ssize_t eth_putFrame(const uint8_t *buf, size_t len)
297 ASSERT(len <= sizeof(tx_buf));
299 /* Check if the transmit buffer is available */
300 while (!(tx_buf_tab[tx_buf_idx].stat & TXS_USED))
301 event_wait(&send_wait);
303 /* Copy the data into the buffer and prepare descriptor */
304 wr_len = MIN(len, (size_t)EMAC_TX_BUFSIZ - tx_buf_offset);
305 memcpy((uint8_t *)tx_buf_tab[tx_buf_idx].addr + tx_buf_offset,
307 tx_buf_offset += wr_len;
312 void eth_sendFrame(void)
314 tx_buf_tab[tx_buf_idx].stat = (tx_buf_offset & TXS_LENGTH_FRAME) |
316 ((tx_buf_idx == EMAC_TX_DESCRIPTORS - 1) ? TXS_WRAP : 0);
317 EMAC_NCR |= BV(EMAC_TSTART);
320 if (++tx_buf_idx >= EMAC_TX_DESCRIPTORS)
324 ssize_t eth_send(const uint8_t *buf, size_t len)
329 len = eth_putFrame(buf, len);
335 static void eth_buf_realign(int idx)
337 /* Empty buffer found. Realign. */
339 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
340 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
342 } while (idx != rx_buf_idx);
345 static size_t __eth_getFrameLen(void)
347 int idx, n = EMAC_RX_BUFFERS;
350 /* Skip empty buffers */
351 while ((n > 0) && !(rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP))
353 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
359 LOG_INFO("no frame found\n");
362 /* Search the start of frame and cleanup fragments */
363 while ((n > 0) && (rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP) &&
364 !(rx_buf_tab[rx_buf_idx].stat & RXS_SOF))
366 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
367 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
373 LOG_INFO("no SOF found\n");
376 /* Search end of frame to evaluate the total frame size */
381 if (UNLIKELY(!(rx_buf_tab[idx].addr & RXBUF_OWNERSHIP)))
383 /* Empty buffer found. Realign. */
384 eth_buf_realign(idx);
387 if (rx_buf_tab[idx].stat & RXS_EOF)
388 return rx_buf_tab[idx].stat & RXS_LENGTH_FRAME;
389 if (UNLIKELY((idx != rx_buf_idx) &&
390 (rx_buf_tab[idx].stat & RXS_SOF)))
392 /* Another start of frame found. Realign. */
393 eth_buf_realign(idx);
396 if (++idx >= EMAC_RX_BUFFERS)
400 LOG_INFO("no EOF found\n");
404 size_t eth_getFrameLen(void)
408 /* Check if there is at least one available frame in the buffer */
411 len = __eth_getFrameLen();
414 /* Wait for RX interrupt */
415 event_wait(&recv_wait);
420 ssize_t eth_getFrame(uint8_t *buf, size_t len)
427 ASSERT(len <= sizeof(rx_buf));
429 /* Copy data from the RX buffer */
430 addr = (uint8_t *)(rx_buf_tab[rx_buf_idx].addr & BUF_ADDRMASK);
431 if (addr + len > &rx_buf[countof(rx_buf)])
433 size_t count = &rx_buf[countof(rx_buf)] - addr;
435 memcpy(buf, addr, count);
436 memcpy(buf + count, rx_buf, len - count);
440 memcpy(buf, addr, len);
442 /* Update descriptors */
445 if (len - rd_len >= EMAC_RX_BUFSIZ)
446 rd_len += EMAC_RX_BUFSIZ;
448 rd_len += len - rd_len;
449 if (UNLIKELY(!(rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP)))
451 LOG_INFO("bad frame found\n");
454 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
455 if (++rx_buf_idx >= EMAC_RX_DESCRIPTORS)
462 ssize_t eth_recv(uint8_t *buf, size_t len)
466 len = MIN(len, eth_getFrameLen());
467 return len ? eth_getFrame(buf, len) : 0;
477 event_initGeneric(&recv_wait);
478 event_initGeneric(&send_wait);
480 // Register interrupt vector
481 IRQ_SAVE_DISABLE(flags);
483 /* Disable all emac interrupts */
484 EMAC_IDR = 0xFFFFFFFF;
486 /* Set the vector. */
487 AIC_SVR(EMAC_ID) = emac_irqHandler;
488 /* Initialize to edge triggered with defined priority. */
489 AIC_SMR(EMAC_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED;
490 /* Clear pending interrupt */
491 AIC_ICCR = BV(EMAC_ID);
492 /* Enable the system IRQ */
493 AIC_IECR = BV(EMAC_ID);
495 /* Enable interrupts */
496 EMAC_IER = EMAC_RX_INTS | EMAC_TX_INTS;