4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
30 * All Rights Reserved.
33 * \brief EMAC driver for AT91SAM7X Family.
35 * \author Daniele Basile <asterix@develer.com>
36 * \author Andrea Righi <arighi@develer.com>
39 #include "cfg/cfg_eth.h"
41 #define LOG_LEVEL ETH_LOG_LEVEL
42 #define LOG_FORMAT ETH_LOG_FORMAT
46 #include <cfg/debug.h>
48 #include <cfg/macros.h>
49 #include <cfg/compiler.h>
51 #include <io/at91sam7.h>
54 #include <cpu/power.h>
55 #include <cpu/types.h>
58 #include <drv/timer.h>
61 #include <mware/event.h>
68 * MAC address configuration (please change this in your project!).
70 * TODO: make this paramater user-configurable from the Wizard.
72 uint8_t mac_addr[] = { 0x11, 0x22, 0x33, 0x44, 0x55, 0x66 };
74 /* Silent Doxygen bug... */
76 static volatile BufDescriptor tx_buf_tab[EMAC_TX_DESCRIPTORS];
78 * NOTE: this buffer should be declared as 'volatile' because it is read by the
79 * hardware. However, this is accessed only via memcpy() that should guarantee
80 * coherency when copying from/to buffers.
82 static uint8_t tx_buf[EMAC_TX_BUFFERS * EMAC_TX_BUFSIZ] ALIGNED(8);
83 static int tx_buf_idx = 0;
85 static volatile BufDescriptor rx_buf_tab[EMAC_RX_DESCRIPTORS];
87 * NOTE: this buffer should be declared as 'volatile' because it is wrote by
88 * the hardware. However, this is accessed only via memcpy() that should
89 * guarantee coherency when copying from/to buffers.
91 static uint8_t rx_buf[EMAC_RX_BUFFERS * EMAC_RX_BUFSIZ] ALIGNED(8);
92 static int rx_buf_idx = 0;
95 static Event recv_wait, send_wait;
97 static DECLARE_ISR(emac_irqHandler)
99 /* Read interrupt status and disable interrupts. */
100 uint32_t isr = EMAC_ISR;
102 /* Receiver interrupt */
103 if ((isr & EMAC_RX_INTS))
105 event_do(&recv_wait);
106 EMAC_RSR = EMAC_RX_INTS;
108 /* Transmitter interrupt */
109 if (isr & EMAC_TX_INTS)
111 event_do(&send_wait);
112 EMAC_TSR = EMAC_TX_INTS;
118 * \brief Read contents of PHY register.
120 * \param reg PHY register number.
122 * \return Contents of the specified register.
124 static uint16_t phy_hw_read(reg8_t reg)
127 EMAC_MAN = EMAC_SOF | EMAC_RW_READ | (NIC_PHY_ADDR << EMAC_PHYA_SHIFT)
128 | ((reg << EMAC_REGA_SHIFT) & EMAC_REGA) | EMAC_CODE;
130 // Wait until PHY logic completed.
131 while (!(EMAC_NSR & BV(EMAC_IDLE)))
134 // Get data from PHY maintenance register.
135 return (uint16_t)(EMAC_MAN & EMAC_DATA);
139 * \brief Write value to PHY register.
141 * \param reg PHY register number.
142 * \param val Value to write.
144 static void phy_hw_write(reg8_t reg, uint16_t val)
146 // PHY write command.
147 EMAC_MAN = EMAC_SOF | EMAC_RW_WRITE | (NIC_PHY_ADDR << EMAC_PHYA_SHIFT)
148 | ((reg << EMAC_REGA_SHIFT) & EMAC_REGA) | EMAC_CODE | val;
150 // Wait until PHY logic completed.
151 while (!(EMAC_NSR & BV(EMAC_IDLE)))
155 static int emac_reset(void)
160 PMC_PCER = BV(PIOA_ID);
161 PMC_PCER = BV(PIOB_ID);
162 PMC_PCER = BV(EMAC_ID);
164 // Disable RMII and TESTMODE by disabling pull-ups.
165 PIOB_PUDR = BV(PHY_COL_RMII_BIT) | BV(PHY_RXDV_TESTMODE_BIT);
167 // Disable PHY power down.
168 PIOB_PER = BV(PHY_PWRDN_BIT);
169 PIOB_OER = BV(PHY_PWRDN_BIT);
170 PIOB_CODR = BV(PHY_PWRDN_BIT);
172 // Toggle external hardware reset pin.
173 RSTC_MR = RSTC_KEY | (1 << RSTC_ERSTL_SHIFT) | BV(RSTC_URSTEN);
174 RSTC_CR = RSTC_KEY | BV(RSTC_EXTRST);
176 while ((RSTC_SR & BV(RSTC_NRSTL)) == 0)
179 // Configure MII port.
180 PIOB_ASR = PHY_MII_PINS;
182 PIOB_PDR = PHY_MII_PINS;
184 // Enable receive and transmit clocks.
185 EMAC_USRIO = BV(EMAC_CLKEN);
187 // Enable management port.
188 EMAC_NCR |= BV(EMAC_MPE);
189 EMAC_NCFGR |= EMAC_CLK_HCLK_32;
191 // Set local MAC address.
192 EMAC_SA1L = (mac_addr[3] << 24) | (mac_addr[2] << 16) |
193 (mac_addr[1] << 8) | mac_addr[0];
194 EMAC_SA1H = (mac_addr[5] << 8) | mac_addr[4];
196 // Wait for PHY ready
199 // Clear MII isolate.
200 phy_hw_read(NIC_PHY_BMCR);
201 phy_cr = phy_hw_read(NIC_PHY_BMCR);
203 phy_cr &= ~NIC_PHY_BMCR_ISOLATE;
204 phy_hw_write(NIC_PHY_BMCR, phy_cr);
206 phy_cr = phy_hw_read(NIC_PHY_BMCR);
208 LOG_INFO("%s: PHY ID %#04x %#04x\n",
210 phy_hw_read(NIC_PHY_ID1), phy_hw_read(NIC_PHY_ID2));
212 // Wait for auto negotiation completed.
213 phy_hw_read(NIC_PHY_BMSR);
216 if (phy_hw_read(NIC_PHY_BMSR) & NIC_PHY_BMSR_ANCOMPL)
221 // Disable management port.
222 EMAC_NCR &= ~BV(EMAC_MPE);
227 static int emac_start(void)
232 for (i = 0; i < EMAC_RX_DESCRIPTORS; i++)
234 addr = (uint32_t)(rx_buf + (i * EMAC_RX_BUFSIZ));
235 rx_buf_tab[i].addr = addr & BUF_ADDRMASK;
237 rx_buf_tab[EMAC_RX_DESCRIPTORS - 1].addr |= RXBUF_WRAP;
239 for (i = 0; i < EMAC_TX_DESCRIPTORS; i++)
241 addr = (uint32_t)(tx_buf + (i * EMAC_TX_BUFSIZ));
242 tx_buf_tab[i].addr = addr & BUF_ADDRMASK;
243 tx_buf_tab[i].stat = TXS_USED;
245 tx_buf_tab[EMAC_TX_DESCRIPTORS - 1].stat = TXS_USED | TXS_WRAP;
247 /* Tell the EMAC where to find the descriptors. */
248 EMAC_RBQP = (uint32_t)rx_buf_tab;
249 EMAC_TBQP = (uint32_t)tx_buf_tab;
251 /* Clear receiver status. */
252 EMAC_RSR = BV(EMAC_OVR) | BV(EMAC_REC) | BV(EMAC_BNA);
254 /* Copy all frames and discard FCS. */
255 EMAC_NCFGR |= BV(EMAC_CAF) | BV(EMAC_DRFCS);
257 /* Enable receiver, transmitter and statistics. */
258 EMAC_NCR |= BV(EMAC_TE) | BV(EMAC_RE) | BV(EMAC_WESTAT);
263 ssize_t eth_send(const uint8_t *buf, size_t len)
270 ASSERT(len <= sizeof(tx_buf));
272 /* Check if the transmit buffer is available */
274 while (!(tx_buf_tab[idx].stat & TXS_USED))
275 event_wait(&send_wait);
277 if (++tx_buf_idx >= EMAC_TX_DESCRIPTORS)
280 /* Copy the data into the buffer and prepare descriptor */
281 wr_len = MIN(len, (size_t)EMAC_TX_BUFSIZ);
282 memcpy((uint8_t *)tx_buf_tab[idx].addr, buf, wr_len);
283 tx_buf_tab[idx].stat = (wr_len & RXS_LENGTH_FRAME) |
284 ((idx == EMAC_TX_DESCRIPTORS - 1) ?
287 EMAC_NCR |= BV(EMAC_TSTART);
292 static size_t eth_getFrameLen(void)
294 int idx, n = EMAC_RX_BUFFERS;
296 /* Skip empty buffers */
297 while ((n > 0) && !(rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP))
299 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
305 LOG_INFO("no frame found\n");
308 /* Search the start of frame and cleanup fragments */
309 while ((n > 0) && (rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP) &&
310 !(rx_buf_tab[rx_buf_idx].stat & RXS_SOF))
312 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
313 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
317 if (UNLIKELY(!(rx_buf_tab[rx_buf_idx].stat & RXS_SOF)))
319 LOG_INFO("no SOF found\n");
322 /* Search end of frame to evaluate the total frame size */
324 while ((n > 0) && (rx_buf_tab[idx].addr & RXBUF_OWNERSHIP))
326 if (UNLIKELY((idx != rx_buf_idx) &&
327 (rx_buf_tab[idx].stat & RXS_SOF)))
329 /* Another start of frame found. Realign. */
331 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
332 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
334 } while (idx != rx_buf_idx);
336 if (rx_buf_tab[idx].stat & RXS_EOF)
337 return rx_buf_tab[idx].stat & RXS_LENGTH_FRAME;
338 if (++idx >= EMAC_RX_BUFFERS)
343 LOG_INFO("no EOF found\n");
347 ssize_t eth_recv(uint8_t *buf, size_t len)
354 ASSERT(len <= sizeof(tx_buf));
356 /* Check if there is at least one available frame in the buffer */
359 size_t frame_len = MIN(len, eth_getFrameLen());
365 /* Wait for RX interrupt */
366 event_wait(&recv_wait);
369 /* Copy data from the RX buffer */
370 addr = (uint8_t *)(rx_buf_tab[rx_buf_idx].addr & BUF_ADDRMASK);
371 if (addr + len > &rx_buf[countof(rx_buf)])
373 size_t count = &rx_buf[countof(rx_buf)] - addr;
375 memcpy(buf, addr, count);
376 memcpy(buf + count, rx_buf, len - count);
380 memcpy(buf, addr, len);
382 /* Update descriptors */
385 if (len - rd_len >= EMAC_RX_BUFSIZ)
386 rd_len += EMAC_RX_BUFSIZ;
388 rd_len += len - rd_len;
389 ASSERT(rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP);
390 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
391 if (++rx_buf_idx >= EMAC_RX_DESCRIPTORS)
404 event_initGeneric(&recv_wait);
405 event_initGeneric(&send_wait);
407 // Register interrupt vector
408 IRQ_SAVE_DISABLE(flags);
410 /* Disable all emac interrupts */
411 EMAC_IDR = 0xFFFFFFFF;
413 /* Set the vector. */
414 AIC_SVR(EMAC_ID) = emac_irqHandler;
415 /* Initialize to edge triggered with defined priority. */
416 AIC_SMR(EMAC_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED;
417 /* Clear pending interrupt */
418 AIC_ICCR = BV(EMAC_ID);
419 /* Enable the system IRQ */
420 AIC_IECR = BV(EMAC_ID);
422 /* Enable interrupts */
423 EMAC_IER = EMAC_RX_INTS | EMAC_TX_INTS;