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29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
30 * All Rights Reserved.
33 * \brief EMAC driver for AT91SAM7X Family.
35 * \author Daniele Basile <asterix@develer.com>
36 * \author Andrea Righi <arighi@develer.com>
39 #include "cfg/cfg_eth.h"
41 #define LOG_LEVEL ETH_LOG_LEVEL
42 #define LOG_FORMAT ETH_LOG_FORMAT
46 #include <cfg/debug.h>
48 #include <cfg/macros.h>
49 #include <cfg/compiler.h>
51 #include <io/at91sam7.h>
54 #include <cpu/power.h>
55 #include <cpu/types.h>
58 #include <drv/timer.h>
61 #include <mware/event.h>
68 * MAC address configuration (please change this in your project!).
70 * TODO: make this paramater user-configurable from the Wizard.
72 uint8_t mac_addr[] = { 0x11, 0x22, 0x33, 0x44, 0x55, 0x66 };
74 static volatile BufDescriptor tx_buf_tab[EMAC_TX_DESCRIPTORS];
76 * NOTE: this buffer should be declared as 'volatile' because it is read by the
77 * hardware. However, this is accessed only via memcpy() that should guarantee
78 * coherency when copying from/to buffers.
80 static uint8_t tx_buf[EMAC_TX_BUFFERS * EMAC_TX_BUFSIZ] ALIGNED(8);
81 static int tx_buf_idx = 0;
83 static volatile BufDescriptor rx_buf_tab[EMAC_RX_DESCRIPTORS];
85 * NOTE: this buffer should be declared as 'volatile' because it is wrote by
86 * the hardware. However, this is accessed only via memcpy() that should
87 * guarantee coherency when copying from/to buffers.
89 static uint8_t rx_buf[EMAC_RX_BUFFERS * EMAC_RX_BUFSIZ] ALIGNED(8);
90 static int rx_buf_idx = 0;
92 static Event recv_wait, send_wait;
94 static DECLARE_ISR(emac_irqHandler)
96 /* Read interrupt status and disable interrupts. */
97 uint32_t isr = EMAC_ISR;
99 /* Receiver interrupt */
100 if ((isr & EMAC_RX_INTS))
102 event_do(&recv_wait);
103 EMAC_RSR = EMAC_RX_INTS;
105 /* Transmitter interrupt */
106 if (isr & EMAC_TX_INTS)
108 event_do(&send_wait);
109 EMAC_TSR = EMAC_TX_INTS;
115 * \brief Read contents of PHY register.
117 * \param reg PHY register number.
119 * \return Contents of the specified register.
121 static uint16_t phy_hw_read(reg8_t reg)
124 EMAC_MAN = EMAC_SOF | EMAC_RW_READ | (NIC_PHY_ADDR << EMAC_PHYA_SHIFT)
125 | ((reg << EMAC_REGA_SHIFT) & EMAC_REGA) | EMAC_CODE;
127 // Wait until PHY logic completed.
128 while (!(EMAC_NSR & BV(EMAC_IDLE)))
131 // Get data from PHY maintenance register.
132 return (uint16_t)(EMAC_MAN & EMAC_DATA);
136 * \brief Write value to PHY register.
138 * \param reg PHY register number.
139 * \param val Value to write.
141 static void phy_hw_write(reg8_t reg, uint16_t val)
143 // PHY write command.
144 EMAC_MAN = EMAC_SOF | EMAC_RW_WRITE | (NIC_PHY_ADDR << EMAC_PHYA_SHIFT)
145 | ((reg << EMAC_REGA_SHIFT) & EMAC_REGA) | EMAC_CODE | val;
147 // Wait until PHY logic completed.
148 while (!(EMAC_NSR & BV(EMAC_IDLE)))
152 static int emac_reset(void)
157 PMC_PCER = BV(PIOA_ID);
158 PMC_PCER = BV(PIOB_ID);
159 PMC_PCER = BV(EMAC_ID);
161 // Disable RMII and TESTMODE by disabling pull-ups.
162 PIOB_PUDR = BV(PHY_COL_RMII_BIT) | BV(PHY_RXDV_TESTMODE_BIT);
164 // Disable PHY power down.
165 PIOB_PER = BV(PHY_PWRDN_BIT);
166 PIOB_OER = BV(PHY_PWRDN_BIT);
167 PIOB_CODR = BV(PHY_PWRDN_BIT);
169 // Toggle external hardware reset pin.
170 RSTC_MR = RSTC_KEY | (1 << RSTC_ERSTL_SHIFT) | BV(RSTC_URSTEN);
171 RSTC_CR = RSTC_KEY | BV(RSTC_EXTRST);
173 while ((RSTC_SR & BV(RSTC_NRSTL)) == 0)
176 // Configure MII port.
177 PIOB_ASR = PHY_MII_PINS;
179 PIOB_PDR = PHY_MII_PINS;
181 // Enable receive and transmit clocks.
182 EMAC_USRIO = BV(EMAC_CLKEN);
184 // Enable management port.
185 EMAC_NCR |= BV(EMAC_MPE);
186 EMAC_NCFGR |= EMAC_CLK_HCLK_32;
188 // Set local MAC address.
189 EMAC_SA1L = (mac_addr[3] << 24) | (mac_addr[2] << 16) |
190 (mac_addr[1] << 8) | mac_addr[0];
191 EMAC_SA1H = (mac_addr[5] << 8) | mac_addr[4];
193 // Wait for PHY ready
196 // Clear MII isolate.
197 phy_hw_read(NIC_PHY_BMCR);
198 phy_cr = phy_hw_read(NIC_PHY_BMCR);
200 phy_cr &= ~NIC_PHY_BMCR_ISOLATE;
201 phy_hw_write(NIC_PHY_BMCR, phy_cr);
203 phy_cr = phy_hw_read(NIC_PHY_BMCR);
205 LOG_INFO("%s: PHY ID %#04x %#04x\n",
207 phy_hw_read(NIC_PHY_ID1), phy_hw_read(NIC_PHY_ID2));
209 // Wait for auto negotiation completed.
210 phy_hw_read(NIC_PHY_BMSR);
213 if (phy_hw_read(NIC_PHY_BMSR) & NIC_PHY_BMSR_ANCOMPL)
218 // Disable management port.
219 EMAC_NCR &= ~BV(EMAC_MPE);
224 static int emac_start(void)
229 for (i = 0; i < EMAC_RX_DESCRIPTORS; i++)
231 addr = (uint32_t)(rx_buf + (i * EMAC_RX_BUFSIZ));
232 rx_buf_tab[i].addr = addr & BUF_ADDRMASK;
234 rx_buf_tab[EMAC_RX_DESCRIPTORS - 1].addr |= RXBUF_WRAP;
236 for (i = 0; i < EMAC_TX_DESCRIPTORS; i++)
238 addr = (uint32_t)(tx_buf + (i * EMAC_TX_BUFSIZ));
239 tx_buf_tab[i].addr = addr & BUF_ADDRMASK;
240 tx_buf_tab[i].stat = TXS_USED;
242 tx_buf_tab[EMAC_TX_DESCRIPTORS - 1].stat = TXS_USED | TXS_WRAP;
244 /* Tell the EMAC where to find the descriptors. */
245 EMAC_RBQP = (uint32_t)rx_buf_tab;
246 EMAC_TBQP = (uint32_t)tx_buf_tab;
248 /* Clear receiver status. */
249 EMAC_RSR = BV(EMAC_OVR) | BV(EMAC_REC) | BV(EMAC_BNA);
251 /* Copy all frames and discard FCS. */
252 EMAC_NCFGR |= BV(EMAC_CAF) | BV(EMAC_DRFCS);
254 /* Enable receiver, transmitter and statistics. */
255 EMAC_NCR |= BV(EMAC_TE) | BV(EMAC_RE) | BV(EMAC_WESTAT);
260 ssize_t eth_send(const uint8_t *buf, size_t len)
267 ASSERT(len <= sizeof(tx_buf));
269 /* Check if the transmit buffer is available */
271 while (!(tx_buf_tab[idx].stat & TXS_USED))
272 event_wait(&send_wait);
274 if (++tx_buf_idx >= EMAC_TX_DESCRIPTORS)
277 /* Copy the data into the buffer and prepare descriptor */
278 wr_len = MIN(len, (size_t)EMAC_TX_BUFSIZ);
279 memcpy((uint8_t *)tx_buf_tab[idx].addr, buf, wr_len);
280 tx_buf_tab[idx].stat = (wr_len & RXS_LENGTH_FRAME) |
281 ((idx == EMAC_TX_DESCRIPTORS - 1) ?
284 EMAC_NCR |= BV(EMAC_TSTART);
289 static size_t eth_getFrameLen(void)
291 int idx, n = EMAC_RX_BUFFERS;
293 /* Skip empty buffers */
294 while ((n > 0) && !(rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP))
296 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
302 LOG_INFO("no frame found\n");
305 /* Search the start of frame and cleanup fragments */
306 while ((n > 0) && (rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP) &&
307 !(rx_buf_tab[rx_buf_idx].stat & RXS_SOF))
309 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
310 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
314 if (UNLIKELY(!(rx_buf_tab[rx_buf_idx].stat & RXS_SOF)))
316 LOG_INFO("no SOF found\n");
319 /* Search end of frame to evaluate the total frame size */
321 while ((n > 0) && (rx_buf_tab[idx].addr & RXBUF_OWNERSHIP))
323 if (UNLIKELY((idx != rx_buf_idx) &&
324 (rx_buf_tab[idx].stat & RXS_SOF)))
326 /* Another start of frame found. Realign. */
328 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
329 if (++rx_buf_idx >= EMAC_RX_BUFFERS)
331 } while (idx != rx_buf_idx);
333 if (rx_buf_tab[idx].stat & RXS_EOF)
334 return rx_buf_tab[idx].stat & RXS_LENGTH_FRAME;
335 if (++idx >= EMAC_RX_BUFFERS)
340 LOG_INFO("no EOF found\n");
344 ssize_t eth_recv(uint8_t *buf, size_t len)
351 ASSERT(len <= sizeof(tx_buf));
353 /* Check if there is at least one available frame in the buffer */
356 size_t frame_len = MIN(len, eth_getFrameLen());
362 /* Wait for RX interrupt */
363 event_wait(&recv_wait);
366 /* Copy data from the RX buffer */
367 addr = (uint8_t *)(rx_buf_tab[rx_buf_idx].addr & BUF_ADDRMASK);
368 if (addr + len > &rx_buf[countof(rx_buf)])
370 size_t count = &rx_buf[countof(rx_buf)] - addr;
372 memcpy(buf, addr, count);
373 memcpy(buf + count, rx_buf, len - count);
377 memcpy(buf, addr, len);
379 /* Update descriptors */
382 if (len - rd_len >= EMAC_RX_BUFSIZ)
383 rd_len += EMAC_RX_BUFSIZ;
385 rd_len += len - rd_len;
386 ASSERT(rx_buf_tab[rx_buf_idx].addr & RXBUF_OWNERSHIP);
387 rx_buf_tab[rx_buf_idx].addr &= ~RXBUF_OWNERSHIP;
388 if (++rx_buf_idx >= EMAC_RX_DESCRIPTORS)
401 event_initGeneric(&recv_wait);
402 event_initGeneric(&send_wait);
404 // Register interrupt vector
405 IRQ_SAVE_DISABLE(flags);
407 /* Disable all emac interrupts */
408 EMAC_IDR = 0xFFFFFFFF;
410 /* Set the vector. */
411 AIC_SVR(EMAC_ID) = emac_irqHandler;
412 /* Initialize to edge triggered with defined priority. */
413 AIC_SMR(EMAC_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED;
414 /* Clear pending interrupt */
415 AIC_ICCR = BV(EMAC_ID);
416 /* Enable the system IRQ */
417 AIC_IECR = BV(EMAC_ID);
419 /* Enable interrupts */
420 EMAC_IER = EMAC_RX_INTS | EMAC_TX_INTS;