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29 * Copyright 2009 Develer S.r.l. (http://www.develer.com/)
30 * All Rights Reserved.
33 * \brief EMAC driver for AT91SAM7X Family, interface.
35 * \author Daniele Basile <asterix@develer.com>
36 * \author Andrea Righi <arighi@develer.com>
42 // Settings and definition for DAVICOM 9161A
44 #define NIC_PHY_ADDR 31
47 #define NIC_PHY_BMCR 0x00 // Basic mode control register.
48 #define NIC_PHY_BMCR_COLTEST 0x0080 // Collision test.
49 #define NIC_PHY_BMCR_FDUPLEX 0x0100 // Full duplex mode.
50 #define NIC_PHY_BMCR_ANEGSTART 0x0200 // Restart auto negotiation.
51 #define NIC_PHY_BMCR_ISOLATE 0x0400 // Isolate from MII.
52 #define NIC_PHY_BMCR_PWRDN 0x0800 // Power-down.
53 #define NIC_PHY_BMCR_ANEGENA 0x1000 // Enable auto negotiation.
54 #define NIC_PHY_BMCR_100MBPS 0x2000 // Select 100 Mbps.
55 #define NIC_PHY_BMCR_LOOPBACK 0x4000 // Enable loopback mode.
56 #define NIC_PHY_BMCR_RESET 0x8000 // Software reset.
58 #define NIC_PHY_BMSR 0x01 // Basic mode status register.
59 #define NIC_PHY_BMSR_ANCOMPL 0x0020 // Auto negotiation complete.
60 #define NIC_PHY_BMSR_ANEGCAPABLE 0x0008 // Able to do auto-negotiation
61 #define NIC_PHY_BMSR_LINKSTAT 0x0004 // Link status.
63 #define NIC_PHY_ID1 0x02 // PHY identifier register 1.
64 #define NIC_PHY_ID2 0x03 // PHY identifier register 2.
65 #define NIC_PHY_ANAR 0x04 // Auto negotiation advertisement register.
66 #define NIC_PHY_ANLPAR 0x05 // Auto negotiation link partner availability register.
67 #define NIC_PHY_ANER 0x06 // Auto negotiation expansion register.
69 // Pin definition for DAVICOM 9161A
70 // See schematic for at91sam7x-ek evalution board
71 #define PHY_TXCLK_ISOLATE_BIT 0
72 #define PHY_REFCLK_XT2_BIT 0
73 #define PHY_TXEN_BIT 1
74 #define PHY_TXD0_BIT 2
75 #define PHY_TXD1_BIT 3
76 #define PHY_CRS_AD4_BIT 4
77 #define PHY_RXD0_AD0_BIT 5
78 #define PHY_RXD1_AD1_BIT 6
79 #define PHY_RXER_RXD4_RPTR_BIT 7
81 #define PHY_MDIO_BIT 9
82 #define PHY_TXD2_BIT 10
83 #define PHY_TXD3_BIT 11
84 #define PHY_TXER_TXD4_BIT 12
85 #define PHY_RXD2_AD2_BIT 13
86 #define PHY_RXD3_AD3_BIT 14
87 #define PHY_RXDV_TESTMODE_BIT 15
88 #define PHY_COL_RMII_BIT 16
89 #define PHY_RXCLK_10BTSER_BIT 17
90 #define PHY_PWRDN_BIT 18
91 #define PHY_MDINTR_BIT 26
93 #define PHY_MII_PINS BV(PHY_REFCLK_XT2_BIT) \
97 | BV(PHY_CRS_AD4_BIT) \
98 | BV(PHY_RXD0_AD0_BIT) \
99 | BV(PHY_RXD1_AD1_BIT) \
100 | BV(PHY_RXER_RXD4_RPTR_BIT) \
105 | BV(PHY_TXER_TXD4_BIT) \
106 | BV(PHY_RXD2_AD2_BIT) \
107 | BV(PHY_RXD3_AD3_BIT) \
108 | BV(PHY_RXDV_TESTMODE_BIT) \
109 | BV(PHY_COL_RMII_BIT) \
110 | BV(PHY_RXCLK_10BTSER_BIT)
113 #define EMAC_TX_BUFSIZ 1518 //!!! Don't change this
114 #define EMAC_TX_BUFFERS 1 //!!! Don't change this
115 #define EMAC_TX_DESCRIPTORS EMAC_TX_BUFFERS
117 #define EMAC_RX_BUFFERS 32 //!!! Don't change this
118 #define EMAC_RX_BUFSIZ 128 //!!! Don't change this
119 #define EMAC_RX_DESCRIPTORS EMAC_RX_BUFFERS
121 // Flag to manage local tx buffer
122 #define TXS_USED 0x80000000 //Used buffer.
123 #define TXS_WRAP 0x40000000 //Last descriptor.
124 #define TXS_ERROR 0x20000000 //Retry limit exceeded.
125 #define TXS_UNDERRUN 0x10000000 //Transmit underrun.
126 #define TXS_NO_BUFFER 0x08000000 //Buffer exhausted.
127 #define TXS_NO_CRC 0x00010000 //CRC not appended.
128 #define TXS_LAST_BUFF 0x00008000 //Last buffer of frame.
129 #define TXS_LENGTH_FRAME 0x000007FF // Length of frame including FCS.
131 // Flag to manage local rx buffer
132 #define RXBUF_OWNERSHIP 0x00000001
133 #define RXBUF_WRAP 0x00000002
135 #define BUF_ADDRMASK 0xFFFFFFFC
137 #define RXS_BROADCAST_ADDR 0x80000000 // Broadcast address detected.
138 #define RXS_MULTICAST_HASH 0x40000000 // Multicast hash match.
139 #define RXS_UNICAST_HASH 0x20000000 // Unicast hash match.
140 #define RXS_EXTERNAL_ADDR 0x10000000 // External address match.
141 #define RXS_SA1_ADDR 0x04000000 // Specific address register 1 match.
142 #define RXS_SA2_ADDR 0x02000000 // Specific address register 2 match.
143 #define RXS_SA3_ADDR 0x01000000 // Specific address register 3 match.
144 #define RXS_SA4_ADDR 0x00800000 // Specific address register 4 match.
145 #define RXS_TYPE_ID 0x00400000 // Type ID match.
146 #define RXS_VLAN_TAG 0x00200000 // VLAN tag detected.
147 #define RXS_PRIORITY_TAG 0x00100000 // Priority tag detected.
148 #define RXS_VLAN_PRIORITY 0x000E0000 // VLAN priority.
149 #define RXS_CFI_IND 0x00010000 // Concatenation format indicator.
150 #define RXS_EOF 0x00008000 // End of frame.
151 #define RXS_SOF 0x00004000 // Start of frame.
152 #define RXS_RBF_OFFSET 0x00003000 // Receive buffer offset mask.
153 #define RXS_LENGTH_FRAME 0x000007FF // Length of frame including FCS.
155 #define EMAC_RSR_BITS (BV(EMAC_BNA) | BV(EMAC_REC) | BV(EMAC_OVR))
156 #define EMAC_TSR_BITS (BV(EMAC_UBR) | BV(EMAC_COL) | BV(EMAC_RLES) | \
157 BV(EMAC_BEX) | BV(EMAC_COMP) | BV(EMAC_UND))
159 typedef struct BufDescriptor
161 volatile uint32_t addr;
162 volatile uint32_t stat;
165 #endif /* ETH_AT91_H */