4 * This file is part of BeRTOS.
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14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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21 * library without restriction. Specifically, if other files instantiate
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29 * Copyright 2008 Develer S.r.l. (http://www.develer.com/)
34 * \brief PWM hardware-specific implementation
38 * \author Daniele Basile <asterix@develer.com>
42 #include "hw/pwm_map.h"
43 #include "hw/hw_cpu.h"
44 #include "cfg/cfg_pwm.h"
46 // Define logging setting (for cfg/log.h module).
47 #define LOG_LEVEL PWM_LOG_LEVEL
48 #define LOG_VERBOSITY PWM_LOG_VERBOSITY
51 #include <cfg/macros.h>
52 #include <cfg/debug.h>
58 * Register structure for pwm driver.
59 * This array content all data and register pointer
60 * to manage pwm peripheral device.
62 static PwmChannel pwm_map[PWM_CNT] =
68 .mode_reg = &PWM_CMR0,
69 .duty_reg = &PWM_CDTY0,
70 .period_reg = &PWM_CPRD0,
71 .update_reg = &PWM_CUPD0,
77 .mode_reg = &PWM_CMR1,
78 .duty_reg = &PWM_CDTY1,
79 .period_reg = &PWM_CPRD1,
80 .update_reg = &PWM_CUPD1,
86 .mode_reg = &PWM_CMR2,
87 .duty_reg = &PWM_CDTY2,
88 .period_reg = &PWM_CPRD2,
89 .update_reg = &PWM_CUPD2,
95 .mode_reg = &PWM_CMR3,
96 .duty_reg = &PWM_CDTY3,
97 .period_reg = &PWM_CPRD3,
98 .update_reg = &PWM_CUPD3,
104 * Get preiod from select channel
108 pwm_period_t pwm_hw_getPeriod(PwmDev dev)
110 return *pwm_map[dev].period_reg;
114 * Set pwm waveform frequecy.
118 void pwm_hw_setFrequency(PwmDev dev, uint32_t freq)
122 for(int i = 0; i <= PWM_HW_MAX_PRESCALER_STEP; i++)
124 period = CLOCK_FREQ / (BV(i) * freq);
125 // LOG_INFO("period[%ld], prescale[%d]\n", period, i);
126 if ((period < PWM_HW_MAX_PERIOD) && (period != 0))
128 //Clean previous channel prescaler, and set new
129 *pwm_map[dev].mode_reg &= ~PWM_CPRE_MCK_MASK;
130 *pwm_map[dev].mode_reg |= i;
132 *pwm_map[dev].period_reg = period;
137 LOG_INFO("PWM ch[%d] period[%ld]\n", dev, period);
141 * Set pwm duty cycle.
143 * \a duty value 0 - 2^16
145 void pwm_hw_setDutyUnlock(PwmDev dev, uint16_t duty)
147 ASSERT(duty <= (uint16_t)*pwm_map[dev].period_reg);
151 * WARNING: is forbidden to write 0 to duty cycle value,
152 * and so for duty = 0 we must enable PIO and clear output!
156 PWM_PIO_PER = pwm_map[dev].pwm_pin;
157 pwm_map[dev].duty_zero = true;
163 * If polarity flag is true we must invert
166 if (pwm_map[dev].pol)
168 duty = (uint16_t)*pwm_map[dev].period_reg - duty;
169 LOG_INFO("Inverted duty[%d], pol[%d]\n", duty, pwm_map[dev].pol);
172 PWM_PIO_PDR = pwm_map[dev].pwm_pin;
173 *pwm_map[dev].update_reg = duty;
174 pwm_map[dev].duty_zero = false;
179 LOG_INFO("PWM ch[%d] duty[%d], period[%ld]\n", dev, duty, *pwm_map[dev].period_reg);
184 * Enable select pwm channel
186 void pwm_hw_enable(PwmDev dev)
188 if (!pwm_map[dev].duty_zero)
189 PWM_PIO_PDR = pwm_map[dev].pwm_pin;
193 * Disable select pwm channel
195 void pwm_hw_disable(PwmDev dev)
197 PWM_PIO_PER = pwm_map[dev].pwm_pin;
201 * Set PWM polarity to select pwm channel
203 void pwm_hw_setPolarity(PwmDev dev, bool pol)
205 pwm_map[dev].pol = pol;
206 LOG_INFO("Set pol[%d]\n", pwm_map[dev].pol);
212 void pwm_hw_init(void)
217 * WARNING: is forbidden to write 0 to duty cycle value,
218 * and so for duty = 0 we must enable PIO and clear output!
219 * - clear PIO outputs
220 * - enable PIO outputs
221 * - Disable PIO and enable PWM functions
224 PWM_PIO_CODR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
225 PWM_PIO_OER = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
226 PWM_PIO_PDR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
227 PWM_PIO_ABSR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
228 PMC_PCER |= BV(PWMC_ID);
230 /* Disable all channels. */
231 PWM_DIS = 0xFFFFFFFF;
232 /* Disable prescalers A and B */
237 * - set period alidned to left
238 * - set output waveform to start at high level
239 * - allow duty cycle modify at next period event
241 for (int ch = 0; ch < PWM_CNT; ch++)
243 *pwm_map[ch].mode_reg = 0;
244 *pwm_map[ch].mode_reg = BV(PWM_CPOL);