4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2008 Develer S.r.l. (http://www.develer.com/)
34 * \brief PWM hardware-specific implementation
38 * \author Daniele Basile <asterix@develer.com>
44 #include "appconfig.h"
46 #include <cfg/macros.h>
47 #include <cfg/debug.h>
53 * Register structure for pwm driver.
54 * This array content all data and register pointer
55 * to manage pwm peripheral device.
57 static PwmChannel pwm_map[PWM_CNT] =
62 .mode_reg = &PWM_CMR0,
63 .duty_reg = &PWM_CDTY0,
64 .period_reg = &PWM_CPRD0,
65 .update_reg = &PWM_CUPD0,
70 .mode_reg = &PWM_CMR1,
71 .duty_reg = &PWM_CDTY1,
72 .period_reg = &PWM_CPRD1,
73 .update_reg = &PWM_CUPD1,
78 .mode_reg = &PWM_CMR2,
79 .duty_reg = &PWM_CDTY2,
80 .period_reg = &PWM_CPRD2,
81 .update_reg = &PWM_CUPD2,
86 .mode_reg = &PWM_CMR3,
87 .duty_reg = &PWM_CDTY3,
88 .period_reg = &PWM_CPRD3,
89 .update_reg = &PWM_CUPD3,
95 * Get preiod from select channel
99 pwm_period_t pwm_hw_getPeriod(PwmDev dev)
101 return *pwm_map[dev].period_reg;
105 * Set pwm waveform frequecy.
109 void pwm_hw_setFrequency(PwmDev dev, uint32_t freq)
113 for(int i = 0; i <= PWM_HW_MAX_PRESCALER_STEP; i++)
115 period = CLOCK_FREQ / (BV(i) * freq);
116 // TRACEMSG("period[%d], prescale[%d]", period, i);
117 if ((period < PWM_HW_MAX_PERIOD) && (period != 0))
119 //Clean previous channel prescaler, and set new
120 *pwm_map[dev].mode_reg &= ~PWM_CPRE_MCK_MASK;
121 *pwm_map[dev].mode_reg |= i;
123 *pwm_map[dev].period_reg = period;
130 // TRACEMSG("PWM ch[%d] period[%d]", dev, period);
134 * Set pwm duty cycle.
136 * \a duty value 0 - 2^16
138 void pwm_hw_setDutyUnlock(PwmDev dev, uint16_t duty)
140 ASSERT(duty <= (uint16_t)*pwm_map[dev].period_reg);
144 * WARNING: is forbidden to write 0 to duty cycle value,
145 * and so for duty = 0 we must enable PIO and clear output!
149 PWM_PIO_PER = pwm_map[dev].pwm_pin;
150 pwm_map[dev].duty_zero = true;
155 PWM_PIO_PDR = pwm_map[dev].pwm_pin;
156 *pwm_map[dev].update_reg = duty;
157 pwm_map[dev].duty_zero = false;
160 // TRACEMSG("PWM ch[%d] duty[%d], period[%ld]", dev, duty, *pwm_map[dev].period_reg);
165 * Enable select pwm channel
167 void pwm_hw_enable(PwmDev dev)
169 if (!pwm_map[dev].duty_zero)
170 PWM_PIO_PDR = pwm_map[dev].pwm_pin;
174 * Disable select pwm channel
176 void pwm_hw_disable(PwmDev dev)
178 PWM_PIO_PER = pwm_map[dev].pwm_pin;
185 void pwm_hw_init(void)
190 * WARNING: is forbidden to write 0 to duty cycle value,
191 * and so for duty = 0 we must enable PIO and clear output!
192 * - clear PIO outputs
193 * - enable PIO outputs
194 * - Disable PIO and enable PWM functions
197 PWM_PIO_CODR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
198 PWM_PIO_OER = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
199 PWM_PIO_PDR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
200 PWM_PIO_ABSR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
201 PMC_PCER |= BV(PWMC_ID);
203 /* Disable all channels. */
204 PWM_DIS = 0xFFFFFFFF;
205 /* Disable prescalers A and B */
210 * - set period alidned to left
211 * - set output waveform to low level
212 * - allow duty cycle modify at next period event
214 for (int ch = 0; ch < PWM_CNT; ch++)
215 *pwm_map[ch].mode_reg = 0;