4 * This file is part of BeRTOS.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
34 * \brief PWM hardware-specific implementation
36 * \author Daniele Basile <asterix@develer.com>
37 * \author Francesco Sacchi <batt@develer.com>
42 #include <hw/hw_cpufreq.h>
43 #include "cfg/cfg_pwm.h"
45 // Define logging setting (for cfg/log.h module).
46 #define LOG_LEVEL PWM_LOG_LEVEL
47 #define LOG_FORMAT PWM_LOG_FORMAT
50 #include <cfg/macros.h>
51 #include <cfg/debug.h>
56 #define PWM_HW_MAX_PRESCALER_STEP 10
57 #define PWM_HW_MAX_PERIOD 0xFFFF
59 #if CFG_PWM_ENABLE_OLD_API
60 #include "hw/pwm_map.h"
63 * Register structure for pwm driver.
64 * This array content all data and register pointer
65 * to manage pwm peripheral device.
67 static PwmChannel pwm_map[PWM_CNT] =
73 .mode_reg = &PWM_CMR0,
74 .duty_reg = &PWM_CDTY0,
75 .period_reg = &PWM_CPRD0,
76 .update_reg = &PWM_CUPD0,
82 .mode_reg = &PWM_CMR1,
83 .duty_reg = &PWM_CDTY1,
84 .period_reg = &PWM_CPRD1,
85 .update_reg = &PWM_CUPD1,
91 .mode_reg = &PWM_CMR2,
92 .duty_reg = &PWM_CDTY2,
93 .period_reg = &PWM_CPRD2,
94 .update_reg = &PWM_CUPD2,
100 .mode_reg = &PWM_CMR3,
101 .duty_reg = &PWM_CDTY3,
102 .period_reg = &PWM_CPRD3,
103 .update_reg = &PWM_CUPD3,
109 * Get preiod from select channel
113 pwm_period_t pwm_hw_getPeriod(PwmDev dev)
115 return *pwm_map[dev].period_reg;
119 * Set pwm waveform frequecy.
123 void pwm_hw_setFrequency(PwmDev dev, uint32_t freq)
127 for(int i = 0; i <= PWM_HW_MAX_PRESCALER_STEP; i++)
129 period = CPU_FREQ / (BV(i) * freq);
130 LOG_INFO("period[%ld], prescale[%d]\n", period, i);
131 if ((period < PWM_HW_MAX_PERIOD) && (period != 0))
133 //Clean previous channel prescaler, and set new
134 *pwm_map[dev].mode_reg &= ~PWM_CPRE_MCK_MASK;
135 *pwm_map[dev].mode_reg |= i;
137 *pwm_map[dev].period_reg = period;
142 LOG_INFO("PWM ch[%d] period[%ld]\n", dev, period);
146 * Set pwm duty cycle.
148 * \a duty value 0 - 2^16
150 void pwm_hw_setDutyUnlock(PwmDev dev, uint16_t duty)
152 ASSERT(duty <= (uint16_t)*pwm_map[dev].period_reg);
156 * If polarity flag is true we must invert
159 if (pwm_map[dev].pol)
161 duty = (uint16_t)*pwm_map[dev].period_reg - duty;
162 LOG_INFO("Inverted duty[%d], pol[%d]\n", duty, pwm_map[dev].pol);
166 * WARNING: is forbidden to write 0 to duty cycle value,
167 * and so for duty = 0 we must enable PIO and clear output!
171 PWM_PIO_CODR = pwm_map[dev].pwm_pin;
172 PWM_PIO_PER = pwm_map[dev].pwm_pin;
173 pwm_map[dev].duty_zero = true;
177 PWM_PIO_PDR = pwm_map[dev].pwm_pin;
178 PWM_PIO_ABSR = pwm_map[dev].pwm_pin;
180 *pwm_map[dev].update_reg = duty;
181 pwm_map[dev].duty_zero = false;
185 LOG_INFO("PWM ch[%d] duty[%d], period[%ld]\n", dev, duty, *pwm_map[dev].period_reg);
190 * Enable select pwm channel
192 void pwm_hw_enable(PwmDev dev)
194 if (!pwm_map[dev].duty_zero)
196 PWM_PIO_PDR = pwm_map[dev].pwm_pin;
197 PWM_PIO_ABSR = pwm_map[dev].pwm_pin;
202 * Disable select pwm channel
204 void pwm_hw_disable(PwmDev dev)
206 PWM_PIO_PER = pwm_map[dev].pwm_pin;
210 * Set PWM polarity to select pwm channel
212 void pwm_hw_setPolarity(PwmDev dev, bool pol)
214 pwm_map[dev].pol = pol;
215 LOG_INFO("Set pol[%d]\n", pwm_map[dev].pol);
221 void pwm_hw_init(void)
226 * WARNING: is forbidden to write 0 to duty cycle value,
227 * and so for duty = 0 we must enable PIO and clear output!
228 * - clear PIO outputs
229 * - enable PIO outputs
230 * - Disable PIO and enable PWM functions
233 PWM_PIO_CODR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
234 PWM_PIO_OER = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
235 PWM_PIO_PDR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
236 PWM_PIO_ABSR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
237 PMC_PCER |= BV(PWMC_ID);
239 /* Disable all channels. */
240 PWM_DIS = 0xFFFFFFFF;
241 /* Disable prescalers A and B */
246 * - set period alidned to left
247 * - set output waveform to start at high level
248 * - allow duty cycle modify at next period event
250 for (int ch = 0; ch < PWM_CNT; ch++)
252 *pwm_map[ch].mode_reg = 0;
253 *pwm_map[ch].mode_reg = BV(PWM_CPOL);
260 typedef struct PwmChannelRegs
271 * Set pwm waveform frequecy.
273 void pwm_hw_setFrequency(Pwm *ctx, pwm_freq_t freq)
277 for(int i = 0; i <= PWM_HW_MAX_PRESCALER_STEP; i++)
279 period = CPU_FREQ / (BV(i) * freq);
280 LOG_INFO("period[%ld], prescale[%d]\n", period, i);
281 if ((period < PWM_HW_MAX_PERIOD) && (period != 0))
283 //Clear previous channel prescaler, and set new
284 ctx->hw->base->CMR &= ~PWM_CPRE_MCK_MASK;
285 ctx->hw->base->CMR |= i;
288 ctx->hw->base->CPRD = period;
289 ctx->hw->base->CDTY = period;
295 LOG_INFO("PWM ch[%d] period[%ld]\n", ctx->ch, period);
298 pwm_hwreg_t pwm_hw_getPeriod(Pwm *ctx)
300 return ctx->hw->base->CPRD;
304 * Set pwm duty cycle.
306 * duty value 0 - (2^16 - 1)
308 void pwm_hw_setDuty(Pwm *ctx, pwm_hwreg_t hw_duty)
310 ASSERT(hw_duty <= ctx->hw->base->CPRD);
313 * WARNING: is forbidden to write 0 or 1 to duty cycle value,
314 * and so for duty < 2 we must enable PIO and clear output!
319 PWM_PIO_PER = ctx->hw->pwm_pin;
322 PWM_PIO_PDR = ctx->hw->pwm_pin;
324 ctx->hw->base->CUPD = hw_duty;
325 LOG_INFO("PWM ch[%d] duty[%d], period[%ld]\n", ctx->ch, hw_duty, ctx->hw->base->CPRD);
328 static PwmHardware pwm_channels[] =
332 .base = (volatile PwmChannelRegs *)&PWM_CMR0,
336 .base = (volatile PwmChannelRegs *)&PWM_CMR1,
340 .base = (volatile PwmChannelRegs *)&PWM_CMR2,
344 .base = (volatile PwmChannelRegs *)&PWM_CMR3,
351 void pwm_hw_init(Pwm *ctx, unsigned ch)
354 ctx->hw = &pwm_channels[ch];
358 * - clear PIO outputs
359 * - enable PIO outputs
360 * - Enable PWM functions
363 PWM_PIO_CODR = ctx->hw->pwm_pin;
364 PWM_PIO_OER = ctx->hw->pwm_pin;
365 PWM_PIO_PER = ctx->hw->pwm_pin;
366 PWM_PIO_ABSR = ctx->hw->pwm_pin;
368 PMC_PCER |= BV(PWMC_ID);
370 /* Disable prescalers A and B */
375 * WARNING: is forbidden to write 0 or 1 to duty cycle value,
376 * and so for start we set duty to 2.
378 * - set period aligned to left
379 * - set output waveform to start at high level
380 * - allow duty cycle modify at next period event
382 ctx->hw->base->CDTY = 2;
383 ctx->hw->base->CMR = BV(PWM_CPOL);