4 * This file is part of BeRTOS.
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14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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21 * library without restriction. Specifically, if other files instantiate
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26 * invalidate any other reasons why the executable file might be covered by
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29 * Copyright 2008 Develer S.r.l. (http://www.develer.com/)
34 * \brief PWM hardware-specific implementation
37 * \author Daniele Basile <asterix@develer.com>
41 #include "hw/pwm_map.h"
42 #include "hw/hw_cpu.h"
43 #include "cfg/cfg_pwm.h"
45 // Define logging setting (for cfg/log.h module).
46 #define LOG_LEVEL PWM_LOG_LEVEL
47 #define LOG_FORMAT PWM_LOG_FORMAT
50 #include <cfg/macros.h>
51 #include <cfg/debug.h>
57 * Register structure for pwm driver.
58 * This array content all data and register pointer
59 * to manage pwm peripheral device.
61 static PwmChannel pwm_map[PWM_CNT] =
67 .mode_reg = &PWM_CMR0,
68 .duty_reg = &PWM_CDTY0,
69 .period_reg = &PWM_CPRD0,
70 .update_reg = &PWM_CUPD0,
76 .mode_reg = &PWM_CMR1,
77 .duty_reg = &PWM_CDTY1,
78 .period_reg = &PWM_CPRD1,
79 .update_reg = &PWM_CUPD1,
85 .mode_reg = &PWM_CMR2,
86 .duty_reg = &PWM_CDTY2,
87 .period_reg = &PWM_CPRD2,
88 .update_reg = &PWM_CUPD2,
94 .mode_reg = &PWM_CMR3,
95 .duty_reg = &PWM_CDTY3,
96 .period_reg = &PWM_CPRD3,
97 .update_reg = &PWM_CUPD3,
103 * Get preiod from select channel
107 pwm_period_t pwm_hw_getPeriod(PwmDev dev)
109 return *pwm_map[dev].period_reg;
113 * Set pwm waveform frequecy.
117 void pwm_hw_setFrequency(PwmDev dev, uint32_t freq)
121 for(int i = 0; i <= PWM_HW_MAX_PRESCALER_STEP; i++)
123 period = CLOCK_FREQ / (BV(i) * freq);
124 // LOG_INFO("period[%ld], prescale[%d]\n", period, i);
125 if ((period < PWM_HW_MAX_PERIOD) && (period != 0))
127 //Clean previous channel prescaler, and set new
128 *pwm_map[dev].mode_reg &= ~PWM_CPRE_MCK_MASK;
129 *pwm_map[dev].mode_reg |= i;
131 *pwm_map[dev].period_reg = period;
136 LOG_INFO("PWM ch[%d] period[%ld]\n", dev, period);
140 * Set pwm duty cycle.
142 * \a duty value 0 - 2^16
144 void pwm_hw_setDutyUnlock(PwmDev dev, uint16_t duty)
146 ASSERT(duty <= (uint16_t)*pwm_map[dev].period_reg);
150 * WARNING: is forbidden to write 0 to duty cycle value,
151 * and so for duty = 0 we must enable PIO and clear output!
155 PWM_PIO_PER = pwm_map[dev].pwm_pin;
156 pwm_map[dev].duty_zero = true;
162 * If polarity flag is true we must invert
165 if (pwm_map[dev].pol)
167 duty = (uint16_t)*pwm_map[dev].period_reg - duty;
168 LOG_INFO("Inverted duty[%d], pol[%d]\n", duty, pwm_map[dev].pol);
171 PWM_PIO_PDR = pwm_map[dev].pwm_pin;
172 *pwm_map[dev].update_reg = duty;
173 pwm_map[dev].duty_zero = false;
178 LOG_INFO("PWM ch[%d] duty[%d], period[%ld]\n", dev, duty, *pwm_map[dev].period_reg);
183 * Enable select pwm channel
185 void pwm_hw_enable(PwmDev dev)
187 if (!pwm_map[dev].duty_zero)
188 PWM_PIO_PDR = pwm_map[dev].pwm_pin;
192 * Disable select pwm channel
194 void pwm_hw_disable(PwmDev dev)
196 PWM_PIO_PER = pwm_map[dev].pwm_pin;
200 * Set PWM polarity to select pwm channel
202 void pwm_hw_setPolarity(PwmDev dev, bool pol)
204 pwm_map[dev].pol = pol;
205 LOG_INFO("Set pol[%d]\n", pwm_map[dev].pol);
211 void pwm_hw_init(void)
216 * WARNING: is forbidden to write 0 to duty cycle value,
217 * and so for duty = 0 we must enable PIO and clear output!
218 * - clear PIO outputs
219 * - enable PIO outputs
220 * - Disable PIO and enable PWM functions
223 PWM_PIO_CODR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
224 PWM_PIO_OER = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
225 PWM_PIO_PDR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
226 PWM_PIO_ABSR = BV(PWM0) | BV(PWM1) | BV(PWM2) | BV(PWM3);
227 PMC_PCER |= BV(PWMC_ID);
229 /* Disable all channels. */
230 PWM_DIS = 0xFFFFFFFF;
231 /* Disable prescalers A and B */
236 * - set period alidned to left
237 * - set output waveform to start at high level
238 * - allow duty cycle modify at next period event
240 for (int ch = 0; ch < PWM_CNT; ch++)
242 *pwm_map[ch].mode_reg = 0;
243 *pwm_map[ch].mode_reg = BV(PWM_CPOL);