4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2000 Bernie Innocenti <bernie@codewiz.org>
34 * \brief ARM UART and SPI I/O driver
38 * \author Daniele Basile <asterix@develer.com>
41 #include "hw/hw_ser.h" /* Required for bus macros overrides */
42 #include <hw/hw_cpufreq.h> /* CPU_FREQ */
44 #include "cfg/cfg_ser.h"
45 #include <cfg/debug.h>
53 #include <drv/ser_p.h>
55 #include <struct/fifobuf.h>
58 #define SERIRQ_PRIORITY 4 ///< default priority for serial irqs.
61 * \name Overridable serial bus hooks
63 * These can be redefined in hw.h to implement
64 * special bus policies such as half-duplex, 485, etc.
68 * TXBEGIN TXCHAR TXEND TXOFF
69 * | __________|__________ | |
72 * ______ __ __ __ __ __ __ ________________
73 * \/ \/ \/ \/ \/ \/ \/
74 * ______/\__/\__/\__/\__/\__/\__/
81 #ifndef SER_UART0_BUS_TXINIT
83 * Default TXINIT macro - invoked in uart0_init()
85 * - Disable GPIO on USART0 tx/rx pins
87 #if !CPU_ARM_SAM7S_LARGE && !CPU_ARM_SAM7X
88 #warning Check USART0 pins!
90 #define SER_UART0_BUS_TXINIT do { \
91 PIOA_PDR = BV(RXD0) | BV(TXD0); \
96 #ifndef SER_UART0_BUS_TXBEGIN
98 * Invoked before starting a transmission
100 #define SER_UART0_BUS_TXBEGIN
103 #ifndef SER_UART0_BUS_TXCHAR
105 * Invoked to send one character.
107 #define SER_UART0_BUS_TXCHAR(c) do { \
112 #ifndef SER_UART0_BUS_TXEND
114 * Invoked as soon as the txfifo becomes empty
116 #define SER_UART0_BUS_TXEND
119 /* End USART0 macros */
121 #ifndef SER_UART1_BUS_TXINIT
123 * Default TXINIT macro - invoked in uart1_init()
125 * - Disable GPIO on USART1 tx/rx pins
127 #if !CPU_ARM_SAM7S_LARGE && !CPU_ARM_SAM7X
128 #warning Check USART1 pins!
130 #define SER_UART1_BUS_TXINIT do { \
131 PIOA_PDR = BV(RXD1) | BV(TXD1); \
136 #ifndef SER_UART1_BUS_TXBEGIN
138 * Invoked before starting a transmission
140 #define SER_UART1_BUS_TXBEGIN
143 #ifndef SER_UART1_BUS_TXCHAR
145 * Invoked to send one character.
147 #define SER_UART1_BUS_TXCHAR(c) do { \
152 #ifndef SER_UART1_BUS_TXEND
154 * Invoked as soon as the txfifo becomes empty
156 #define SER_UART1_BUS_TXEND
160 * \name Overridable SPI hooks
162 * These can be redefined in hw.h to implement
163 * special bus policies such as slave select pin handling, etc.
168 #ifndef SER_SPI0_BUS_TXINIT
170 * Default TXINIT macro - invoked in spi_init()
171 * The default is no action.
173 #define SER_SPI0_BUS_TXINIT
176 #ifndef SER_SPI0_BUS_TXCLOSE
178 * Invoked after the last character has been transmitted.
179 * The default is no action.
181 #define SER_SPI0_BUS_TXCLOSE
186 #ifndef SER_SPI1_BUS_TXINIT
188 * Default TXINIT macro - invoked in spi_init()
189 * The default is no action.
191 #define SER_SPI1_BUS_TXINIT
194 #ifndef SER_SPI1_BUS_TXCLOSE
196 * Invoked after the last character has been transmitted.
197 * The default is no action.
199 #define SER_SPI1_BUS_TXCLOSE
206 * \def CONFIG_SER_STROBE
208 * This is a debug facility that can be used to
209 * monitor SER interrupt activity on an external pin.
211 * To use strobes, redefine the macros SER_STROBE_ON,
212 * SER_STROBE_OFF and SER_STROBE_INIT and set
213 * CONFIG_SER_STROBE to 1.
215 #if !defined(CONFIG_SER_STROBE) || !CONFIG_SER_STROBE
216 #define SER_STROBE_ON do {/*nop*/} while(0)
217 #define SER_STROBE_OFF do {/*nop*/} while(0)
218 #define SER_STROBE_INIT do {/*nop*/} while(0)
222 /* From the high-level serial driver */
223 extern struct Serial *ser_handles[SER_CNT];
225 /* TX and RX buffers */
226 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
227 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
229 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
230 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
232 static unsigned char spi0_txbuffer[CONFIG_SPI0_TXBUFSIZE];
233 static unsigned char spi0_rxbuffer[CONFIG_SPI0_RXBUFSIZE];
235 static unsigned char spi1_txbuffer[CONFIG_SPI1_TXBUFSIZE];
236 static unsigned char spi1_rxbuffer[CONFIG_SPI1_RXBUFSIZE];
240 * Internal hardware state structure
242 * The \a sending variable is true while the transmission
243 * interrupt is retriggering itself.
245 * For the USARTs the \a sending flag is useful for taking specific
246 * actions before sending a burst of data, at the start of a trasmission
247 * but not before every char sent.
249 * For the SPI, this flag is necessary because the SPI sends and receives
250 * bytes at the same time and the SPI IRQ is unique for send/receive.
251 * The only way to start transmission is to write data in SPDR (this
252 * is done by spi_starttx()). We do this *only* if a transfer is
253 * not already started.
257 struct SerialHardware hw;
258 volatile bool sending;
261 static void uart0_irq_dispatcher(void);
262 static void uart1_irq_dispatcher(void);
263 static void spi0_irq_handler(void);
265 static void spi1_irq_handler(void);
268 * Callbacks for USART0
270 static void uart0_init(
271 UNUSED_ARG(struct SerialHardware *, _hw),
272 UNUSED_ARG(struct Serial *, ser))
274 US0_IDR = 0xFFFFFFFF;
275 /* Set the vector. */
276 AIC_SVR(US0_ID) = uart0_irq_dispatcher;
277 /* Initialize to level sensitive with defined priority. */
278 AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | SERIRQ_PRIORITY;
279 PMC_PCER = BV(US0_ID);
283 * - Set serial param: mode Normal, 8bit data, 1bit stop, parity none
284 * - Enable both the receiver and the transmitter
285 * - Enable only the RX complete interrupt
287 US0_CR = BV(US_RSTRX) | BV(US_RSTTX);
288 US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO;
289 US0_CR = BV(US_RXEN) | BV(US_TXEN);
290 US0_IER = BV(US_RXRDY);
292 SER_UART0_BUS_TXINIT;
294 /* Enable the USART IRQ */
295 AIC_IECR = BV(US0_ID);
300 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
302 US0_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
305 static void uart0_enabletxirq(struct SerialHardware *_hw)
307 struct ArmSerial *hw = (struct ArmSerial *)_hw;
310 * WARNING: racy code here! The tx interrupt sets hw->sending to false
311 * when it runs with an empty fifo. The order of statements in the
318 * - Enable the transmitter
319 * - Enable TX empty interrupt
321 SER_UART0_BUS_TXBEGIN;
322 US0_IER = BV(US_TXEMPTY);
326 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
328 /* Compute baud-rate period */
329 US0_BRGR = CPU_FREQ / (16 * rate);
330 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
333 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
335 US0_MR &= ~US_PAR_MASK;
336 /* Set UART parity */
339 case SER_PARITY_NONE:
345 case SER_PARITY_EVEN:
348 US0_MR |= US_PAR_EVEN;
354 US0_MR |= US_PAR_ODD;
363 * Callbacks for USART1
365 static void uart1_init(
366 UNUSED_ARG(struct SerialHardware *, _hw),
367 UNUSED_ARG(struct Serial *, ser))
369 US1_IDR = 0xFFFFFFFF;
370 /* Set the vector. */
371 AIC_SVR(US1_ID) = uart1_irq_dispatcher;
372 /* Initialize to level sensitive with defined priority. */
373 AIC_SMR(US1_ID) = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | SERIRQ_PRIORITY;
374 PMC_PCER = BV(US1_ID);
378 * - Set serial param: mode Normal, 8bit data, 1bit stop, parity none
379 * - Enable both the receiver and the transmitter
380 * - Enable only the RX complete interrupt
382 US1_CR = BV(US_RSTRX) | BV(US_RSTTX);
383 US1_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO;
384 US1_CR = BV(US_RXEN) | BV(US_TXEN);
385 US1_IER = BV(US_RXRDY);
387 SER_UART1_BUS_TXINIT;
389 /* Enable the USART IRQ */
390 AIC_IECR = BV(US1_ID);
395 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
397 US1_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
400 static void uart1_enabletxirq(struct SerialHardware *_hw)
402 struct ArmSerial *hw = (struct ArmSerial *)_hw;
405 * WARNING: racy code here! The tx interrupt sets hw->sending to false
406 * when it runs with an empty fifo. The order of statements in the
413 * - Enable the transmitter
414 * - Enable TX empty interrupt
416 SER_UART1_BUS_TXBEGIN;
417 US1_IER = BV(US_TXEMPTY);
421 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
423 /* Compute baud-rate period */
424 US1_BRGR = CPU_FREQ / (16 * rate);
425 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
428 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
430 US1_MR &= ~US_PAR_MASK;
431 /* Set UART parity */
434 case SER_PARITY_NONE:
440 case SER_PARITY_EVEN:
443 US1_MR |= US_PAR_EVEN;
449 US1_MR |= US_PAR_ODD;
459 static void spi0_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
461 /* Disable PIO on SPI pins */
462 PIOA_PDR = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO);
465 SPI0_CR = BV(SPI_SWRST);
468 * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device,
469 * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0
471 SPI0_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS);
475 * At reset clock division factor is set to 0, that is
476 * *forbidden*. Set SPI clock to minimum to keep it valid.
478 SPI0_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
480 /* Disable all irqs */
481 SPI0_IDR = 0xFFFFFFFF;
482 /* Set the vector. */
483 AIC_SVR(SPI0_ID) = spi0_irq_handler;
484 /* Initialize to edge triggered with defined priority. */
485 AIC_SMR(SPI0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY;
486 /* Enable the USART IRQ */
487 AIC_IECR = BV(SPI0_ID);
488 PMC_PCER = BV(SPI0_ID);
490 /* Enable interrupt on tx buffer empty */
491 SPI0_IER = BV(SPI_TXEMPTY);
494 SPI0_CR = BV(SPI_SPIEN);
502 static void spi0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
505 SPI0_CR = BV(SPI_SPIDIS);
507 /* Disable all irqs */
508 SPI0_IDR = 0xFFFFFFFF;
510 SER_SPI0_BUS_TXCLOSE;
512 /* Enable PIO on SPI pins */
513 PIOA_PER = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO);
516 static void spi0_starttx(struct SerialHardware *_hw)
518 struct ArmSerial *hw = (struct ArmSerial *)_hw;
521 IRQ_SAVE_DISABLE(flags);
523 /* Send data only if the SPI is not already transmitting */
524 if (!hw->sending && !fifo_isempty(&ser_handles[SER_SPI0]->txfifo))
527 SPI0_TDR = fifo_pop(&ser_handles[SER_SPI0]->txfifo);
533 static void spi0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
535 SPI0_CSR0 &= ~SPI_SCBR;
537 ASSERT((uint8_t)DIV_ROUND(CPU_FREQ, rate));
538 SPI0_CSR0 |= DIV_ROUND(CPU_FREQ, rate) << SPI_SCBR_SHIFT;
543 static void spi1_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
545 /* Disable PIO on SPI pins */
546 PIOA_PDR = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO);
549 SPI1_CR = BV(SPI_SWRST);
552 * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device,
553 * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0
555 SPI1_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS);
559 * At reset clock division factor is set to 0, that is
560 * *forbidden*. Set SPI clock to minimum to keep it valid.
562 SPI1_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
564 /* Disable all irqs */
565 SPI1_IDR = 0xFFFFFFFF;
566 /* Set the vector. */
567 AIC_SVR(SPI1_ID) = spi1_irq_handler;
568 /* Initialize to edge triggered with defined priority. */
569 AIC_SMR(SPI1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY;
570 /* Enable the USART IRQ */
571 AIC_IECR = BV(SPI1_ID);
572 PMC_PCER = BV(SPI1_ID);
574 /* Enable interrupt on tx buffer empty */
575 SPI1_IER = BV(SPI_TXEMPTY);
578 SPI1_CR = BV(SPI_SPIEN);
586 static void spi1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
589 SPI1_CR = BV(SPI_SPIDIS);
591 /* Disable all irqs */
592 SPI1_IDR = 0xFFFFFFFF;
594 SER_SPI1_BUS_TXCLOSE;
596 /* Enable PIO on SPI pins */
597 PIOA_PER = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO);
600 static void spi1_starttx(struct SerialHardware *_hw)
602 struct ArmSerial *hw = (struct ArmSerial *)_hw;
605 IRQ_SAVE_DISABLE(flags);
607 /* Send data only if the SPI is not already transmitting */
608 if (!hw->sending && !fifo_isempty(&ser_handles[SER_SPI1]->txfifo))
611 SPI1_TDR = fifo_pop(&ser_handles[SER_SPI1]->txfifo);
617 static void spi1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
619 SPI1_CSR0 &= ~SPI_SCBR;
621 ASSERT((uint8_t)DIV_ROUND(CPU_FREQ, rate));
622 SPI1_CSR0 |= DIV_ROUND(CPU_FREQ, rate) << SPI_SCBR_SHIFT;
626 static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
632 static bool tx_sending(struct SerialHardware* _hw)
634 struct ArmSerial *hw = (struct ArmSerial *)_hw;
638 // FIXME: move into compiler.h? Ditch?
640 #define C99INIT(name,val) .name = val
641 #elif defined(__GNUC__)
642 #define C99INIT(name,val) name: val
644 #warning No designated initializers, double check your code
645 #define C99INIT(name,val) (val)
649 * High-level interface data structures
651 static const struct SerialHardwareVT UART0_VT =
653 C99INIT(init, uart0_init),
654 C99INIT(cleanup, uart0_cleanup),
655 C99INIT(setBaudrate, uart0_setbaudrate),
656 C99INIT(setParity, uart0_setparity),
657 C99INIT(txStart, uart0_enabletxirq),
658 C99INIT(txSending, tx_sending),
661 static const struct SerialHardwareVT UART1_VT =
663 C99INIT(init, uart1_init),
664 C99INIT(cleanup, uart1_cleanup),
665 C99INIT(setBaudrate, uart1_setbaudrate),
666 C99INIT(setParity, uart1_setparity),
667 C99INIT(txStart, uart1_enabletxirq),
668 C99INIT(txSending, tx_sending),
671 static const struct SerialHardwareVT SPI0_VT =
673 C99INIT(init, spi0_init),
674 C99INIT(cleanup, spi0_cleanup),
675 C99INIT(setBaudrate, spi0_setbaudrate),
676 C99INIT(setParity, spi_setparity),
677 C99INIT(txStart, spi0_starttx),
678 C99INIT(txSending, tx_sending),
681 static const struct SerialHardwareVT SPI1_VT =
683 C99INIT(init, spi1_init),
684 C99INIT(cleanup, spi1_cleanup),
685 C99INIT(setBaudrate, spi1_setbaudrate),
686 C99INIT(setParity, spi_setparity),
687 C99INIT(txStart, spi1_starttx),
688 C99INIT(txSending, tx_sending),
692 static struct ArmSerial UARTDescs[SER_CNT] =
696 C99INIT(table, &UART0_VT),
697 C99INIT(txbuffer, uart0_txbuffer),
698 C99INIT(rxbuffer, uart0_rxbuffer),
699 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
700 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
702 C99INIT(sending, false),
706 C99INIT(table, &UART1_VT),
707 C99INIT(txbuffer, uart1_txbuffer),
708 C99INIT(rxbuffer, uart1_rxbuffer),
709 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
710 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
712 C99INIT(sending, false),
717 C99INIT(table, &SPI0_VT),
718 C99INIT(txbuffer, spi0_txbuffer),
719 C99INIT(rxbuffer, spi0_rxbuffer),
720 C99INIT(txbuffer_size, sizeof(spi0_txbuffer)),
721 C99INIT(rxbuffer_size, sizeof(spi0_rxbuffer)),
723 C99INIT(sending, false),
728 C99INIT(table, &SPI1_VT),
729 C99INIT(txbuffer, spi1_txbuffer),
730 C99INIT(rxbuffer, spi1_rxbuffer),
731 C99INIT(txbuffer_size, sizeof(spi1_txbuffer)),
732 C99INIT(rxbuffer_size, sizeof(spi1_rxbuffer)),
734 C99INIT(sending, false),
740 struct SerialHardware *ser_hw_getdesc(int unit)
742 ASSERT(unit < SER_CNT);
743 return &UARTDescs[unit].hw;
747 * Serial 0 TX interrupt handler
749 static void uart0_irq_tx(void)
753 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART0]->txfifo;
755 if (fifo_isempty(txfifo))
758 * - Disable the TX empty interrupts
760 US0_IDR = BV(US_TXEMPTY);
762 UARTDescs[SER_UART0].sending = false;
766 char c = fifo_pop(txfifo);
767 SER_UART0_BUS_TXCHAR(c);
774 * Serial 0 RX complete interrupt handler.
776 static void uart0_irq_rx(void)
780 /* Should be read before US_CRS */
781 ser_handles[SER_UART0]->status |= US0_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
782 US0_CR = BV(US_RSTSTA);
785 struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART0]->rxfifo;
787 if (fifo_isfull(rxfifo))
788 ser_handles[SER_UART0]->status |= SERRF_RXFIFOOVERRUN;
790 fifo_push(rxfifo, c);
796 * Serial IRQ dispatcher for USART0.
798 static void uart0_irq_dispatcher(void) __attribute__ ((interrupt));
799 static void uart0_irq_dispatcher(void)
801 if (US0_CSR & BV(US_RXRDY))
804 if (US0_CSR & BV(US_TXEMPTY))
807 /* Inform hw that we have served the IRQ */
812 * Serial 1 TX interrupt handler
814 static void uart1_irq_tx(void)
818 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART1]->txfifo;
820 if (fifo_isempty(txfifo))
823 * - Disable the TX empty interrupts
825 US1_IDR = BV(US_TXEMPTY);
827 UARTDescs[SER_UART1].sending = false;
831 char c = fifo_pop(txfifo);
832 SER_UART1_BUS_TXCHAR(c);
839 * Serial 1 RX complete interrupt handler.
841 static void uart1_irq_rx(void)
845 /* Should be read before US_CRS */
846 ser_handles[SER_UART1]->status |= US1_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
847 US1_CR = BV(US_RSTSTA);
850 struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART1]->rxfifo;
852 if (fifo_isfull(rxfifo))
853 ser_handles[SER_UART1]->status |= SERRF_RXFIFOOVERRUN;
855 fifo_push(rxfifo, c);
861 * Serial IRQ dispatcher for USART1.
863 static void uart1_irq_dispatcher(void) __attribute__ ((interrupt));
864 static void uart1_irq_dispatcher(void)
866 if (US1_CSR & BV(US_RXRDY))
869 if (US1_CSR & BV(US_TXEMPTY))
872 /* Inform hw that we have served the IRQ */
877 * SPI0 interrupt handler
879 static void spi0_irq_handler(void) __attribute__ ((interrupt));
880 static void spi0_irq_handler(void)
885 /* Read incoming byte. */
886 if (!fifo_isfull(&ser_handles[SER_SPI0]->rxfifo))
887 fifo_push(&ser_handles[SER_SPI0]->rxfifo, c);
891 ser_handles[SER_SPI0]->status |= SERRF_RXFIFOOVERRUN;
895 if (!fifo_isempty(&ser_handles[SER_SPI0]->txfifo))
896 SPI0_TDR = fifo_pop(&ser_handles[SER_SPI0]->txfifo);
898 UARTDescs[SER_SPI0].sending = false;
900 /* Inform hw that we have served the IRQ */
908 * SPI1 interrupt handler
910 static void spi1_irq_handler(void) __attribute__ ((interrupt));
911 static void spi1_irq_handler(void)
916 /* Read incoming byte. */
917 if (!fifo_isfull(&ser_handles[SER_SPI1]->rxfifo))
918 fifo_push(&ser_handles[SER_SPI1]->rxfifo, c);
922 ser_handles[SER_SPI1]->status |= SERRF_RXFIFOOVERRUN;
926 if (!fifo_isempty(&ser_handles[SER_SPI1]->txfifo))
927 SPI1_TDR = fifo_pop(&ser_handles[SER_SPI1]->txfifo);
929 UARTDescs[SER_SPI1].sending = false;
931 /* Inform hw that we have served the IRQ */