4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2000 Bernie Innocenti <bernie@codewiz.org>
34 * \brief ARM UART and SPI I/O driver
38 * \author Daniele Basile <asterix@develer.com>
41 #include "hw/hw_ser.h" /* Required for bus macros overrides */
42 #include <hw/hw_cpufreq.h> /* CPU_FREQ */
44 #include "cfg/cfg_ser.h"
45 #include <cfg/debug.h>
53 #include <drv/ser_p.h>
55 #include <struct/fifobuf.h>
58 #define SERIRQ_PRIORITY 4 ///< default priority for serial irqs.
61 * \name Overridable serial bus hooks
63 * These can be redefined in hw.h to implement
64 * special bus policies such as half-duplex, 485, etc.
68 * TXBEGIN TXCHAR TXEND TXOFF
69 * | __________|__________ | |
72 * ______ __ __ __ __ __ __ ________________
73 * \/ \/ \/ \/ \/ \/ \/
74 * ______/\__/\__/\__/\__/\__/\__/
81 #ifndef SER_UART0_BUS_TXINIT
83 * Default TXINIT macro - invoked in uart0_init()
85 * - Disable GPIO on USART0 tx/rx pins
87 #if !CPU_ARM_SAM7S_LARGE && !CPU_ARM_SAM7X
88 #warning Check USART0 pins!
90 #define SER_UART0_BUS_TXINIT do { \
91 PIOA_PDR = BV(RXD0) | BV(TXD0); \
96 #ifndef SER_UART0_BUS_TXBEGIN
98 * Invoked before starting a transmission
100 #define SER_UART0_BUS_TXBEGIN
103 #ifndef SER_UART0_BUS_TXCHAR
105 * Invoked to send one character.
107 #define SER_UART0_BUS_TXCHAR(c) do { \
112 #ifndef SER_UART0_BUS_TXEND
114 * Invoked as soon as the txfifo becomes empty
116 #define SER_UART0_BUS_TXEND
119 /* End USART0 macros */
121 #ifndef SER_UART1_BUS_TXINIT
123 * Default TXINIT macro - invoked in uart1_init()
125 * - Disable GPIO on USART1 tx/rx pins
127 #if !CPU_ARM_SAM7S_LARGE && !CPU_ARM_SAM7X
128 #warning Check USART1 pins!
130 #define SER_UART1_BUS_TXINIT do { \
131 PIOA_PDR = BV(RXD1) | BV(TXD1); \
136 #ifndef SER_UART1_BUS_TXBEGIN
138 * Invoked before starting a transmission
140 #define SER_UART1_BUS_TXBEGIN
143 #ifndef SER_UART1_BUS_TXCHAR
145 * Invoked to send one character.
147 #define SER_UART1_BUS_TXCHAR(c) do { \
152 #ifndef SER_UART1_BUS_TXEND
154 * Invoked as soon as the txfifo becomes empty
156 #define SER_UART1_BUS_TXEND
160 * \name Overridable SPI hooks
162 * These can be redefined in hw.h to implement
163 * special bus policies such as slave select pin handling, etc.
168 #ifndef SER_SPI0_BUS_TXINIT
170 * Default TXINIT macro - invoked in spi_init()
171 * The default is no action.
173 #define SER_SPI0_BUS_TXINIT
176 #ifndef SER_SPI0_BUS_TXCLOSE
178 * Invoked after the last character has been transmitted.
179 * The default is no action.
181 #define SER_SPI0_BUS_TXCLOSE
186 #ifndef SER_SPI1_BUS_TXINIT
188 * Default TXINIT macro - invoked in spi_init()
189 * The default is no action.
191 #define SER_SPI1_BUS_TXINIT
194 #ifndef SER_SPI1_BUS_TXCLOSE
196 * Invoked after the last character has been transmitted.
197 * The default is no action.
199 #define SER_SPI1_BUS_TXCLOSE
207 /* From the high-level serial driver */
208 extern struct Serial *ser_handles[SER_CNT];
210 /* TX and RX buffers */
211 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
212 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
214 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
215 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
217 static unsigned char spi0_txbuffer[CONFIG_SPI0_TXBUFSIZE];
218 static unsigned char spi0_rxbuffer[CONFIG_SPI0_RXBUFSIZE];
220 static unsigned char spi1_txbuffer[CONFIG_SPI1_TXBUFSIZE];
221 static unsigned char spi1_rxbuffer[CONFIG_SPI1_RXBUFSIZE];
225 * Internal hardware state structure
227 * The \a sending variable is true while the transmission
228 * interrupt is retriggering itself.
230 * For the USARTs the \a sending flag is useful for taking specific
231 * actions before sending a burst of data, at the start of a trasmission
232 * but not before every char sent.
234 * For the SPI, this flag is necessary because the SPI sends and receives
235 * bytes at the same time and the SPI IRQ is unique for send/receive.
236 * The only way to start transmission is to write data in SPDR (this
237 * is done by spi_starttx()). We do this *only* if a transfer is
238 * not already started.
242 struct SerialHardware hw;
243 volatile bool sending;
246 static ISR_PROTO(uart0_irq_dispatcher);
247 static ISR_PROTO(uart1_irq_dispatcher);
248 static ISR_PROTO(spi0_irq_handler);
250 static ISR_PROTO(spi1_irq_handler);
253 * Callbacks for USART0
255 static void uart0_init(
256 UNUSED_ARG(struct SerialHardware *, _hw),
257 UNUSED_ARG(struct Serial *, ser))
259 US0_IDR = 0xFFFFFFFF;
260 /* Set the vector. */
261 AIC_SVR(US0_ID) = uart0_irq_dispatcher;
262 /* Initialize to level sensitive with defined priority. */
263 AIC_SMR(US0_ID) = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | SERIRQ_PRIORITY;
264 PMC_PCER = BV(US0_ID);
268 * - Set serial param: mode Normal, 8bit data, 1bit stop, parity none
269 * - Enable both the receiver and the transmitter
270 * - Enable only the RX complete interrupt
272 US0_CR = BV(US_RSTRX) | BV(US_RSTTX);
273 US0_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO;
274 US0_CR = BV(US_RXEN) | BV(US_TXEN);
275 US0_IER = BV(US_RXRDY);
277 SER_UART0_BUS_TXINIT;
279 /* Enable the USART IRQ */
280 AIC_IECR = BV(US0_ID);
285 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
287 US0_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
290 static void uart0_enabletxirq(struct SerialHardware *_hw)
292 struct ArmSerial *hw = (struct ArmSerial *)_hw;
295 * WARNING: racy code here! The tx interrupt sets hw->sending to false
296 * when it runs with an empty fifo. The order of statements in the
303 * - Enable the transmitter
304 * - Enable TX empty interrupt
306 SER_UART0_BUS_TXBEGIN;
307 US0_IER = BV(US_TXEMPTY);
311 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
313 /* Compute baud-rate period */
314 US0_BRGR = CPU_FREQ / (16 * rate);
315 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
318 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
320 US0_MR &= ~US_PAR_MASK;
321 /* Set UART parity */
324 case SER_PARITY_NONE:
330 case SER_PARITY_EVEN:
333 US0_MR |= US_PAR_EVEN;
339 US0_MR |= US_PAR_ODD;
348 * Callbacks for USART1
350 static void uart1_init(
351 UNUSED_ARG(struct SerialHardware *, _hw),
352 UNUSED_ARG(struct Serial *, ser))
354 US1_IDR = 0xFFFFFFFF;
355 /* Set the vector. */
356 AIC_SVR(US1_ID) = uart1_irq_dispatcher;
357 /* Initialize to level sensitive with defined priority. */
358 AIC_SMR(US1_ID) = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | SERIRQ_PRIORITY;
359 PMC_PCER = BV(US1_ID);
363 * - Set serial param: mode Normal, 8bit data, 1bit stop, parity none
364 * - Enable both the receiver and the transmitter
365 * - Enable only the RX complete interrupt
367 US1_CR = BV(US_RSTRX) | BV(US_RSTTX);
368 US1_MR = US_CHMODE_NORMAL | US_CHRL_8 | US_NBSTOP_1 | US_PAR_NO;
369 US1_CR = BV(US_RXEN) | BV(US_TXEN);
370 US1_IER = BV(US_RXRDY);
372 SER_UART1_BUS_TXINIT;
374 /* Enable the USART IRQ */
375 AIC_IECR = BV(US1_ID);
380 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
382 US1_CR = BV(US_RSTRX) | BV(US_RSTTX) | BV(US_RXDIS) | BV(US_TXDIS) | BV(US_RSTSTA);
385 static void uart1_enabletxirq(struct SerialHardware *_hw)
387 struct ArmSerial *hw = (struct ArmSerial *)_hw;
390 * WARNING: racy code here! The tx interrupt sets hw->sending to false
391 * when it runs with an empty fifo. The order of statements in the
398 * - Enable the transmitter
399 * - Enable TX empty interrupt
401 SER_UART1_BUS_TXBEGIN;
402 US1_IER = BV(US_TXEMPTY);
406 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
408 /* Compute baud-rate period */
409 US1_BRGR = CPU_FREQ / (16 * rate);
410 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
413 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
415 US1_MR &= ~US_PAR_MASK;
416 /* Set UART parity */
419 case SER_PARITY_NONE:
425 case SER_PARITY_EVEN:
428 US1_MR |= US_PAR_EVEN;
434 US1_MR |= US_PAR_ODD;
444 static void spi0_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
446 /* Disable PIO on SPI pins */
447 PIOA_PDR = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO);
450 SPI0_CR = BV(SPI_SWRST);
453 * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device,
454 * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0
456 SPI0_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS);
460 * At reset clock division factor is set to 0, that is
461 * *forbidden*. Set SPI clock to minimum to keep it valid.
463 SPI0_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
465 /* Disable all irqs */
466 SPI0_IDR = 0xFFFFFFFF;
467 /* Set the vector. */
468 AIC_SVR(SPI0_ID) = spi0_irq_handler;
469 /* Initialize to edge triggered with defined priority. */
470 AIC_SMR(SPI0_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY;
471 /* Enable the USART IRQ */
472 AIC_IECR = BV(SPI0_ID);
473 PMC_PCER = BV(SPI0_ID);
475 /* Enable interrupt on tx buffer empty */
476 SPI0_IER = BV(SPI_TXEMPTY);
479 SPI0_CR = BV(SPI_SPIEN);
487 static void spi0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
490 SPI0_CR = BV(SPI_SPIDIS);
492 /* Disable all irqs */
493 SPI0_IDR = 0xFFFFFFFF;
495 SER_SPI0_BUS_TXCLOSE;
497 /* Enable PIO on SPI pins */
498 PIOA_PER = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO);
501 static void spi0_starttx(struct SerialHardware *_hw)
503 struct ArmSerial *hw = (struct ArmSerial *)_hw;
506 IRQ_SAVE_DISABLE(flags);
508 /* Send data only if the SPI is not already transmitting */
509 if (!hw->sending && !fifo_isempty(&ser_handles[SER_SPI0]->txfifo))
512 SPI0_TDR = fifo_pop(&ser_handles[SER_SPI0]->txfifo);
518 static void spi0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
520 SPI0_CSR0 &= ~SPI_SCBR;
522 ASSERT((uint8_t)DIV_ROUND(CPU_FREQ, rate));
523 SPI0_CSR0 |= DIV_ROUND(CPU_FREQ, rate) << SPI_SCBR_SHIFT;
528 static void spi1_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
530 /* Disable PIO on SPI pins */
531 PIOA_PDR = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO);
533 /* SPI1 pins are on B peripheral function! */
534 PIOA_BSR = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO);
537 SPI1_CR = BV(SPI_SWRST);
540 * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device,
541 * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0
543 SPI1_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS);
547 * At reset clock division factor is set to 0, that is
548 * *forbidden*. Set SPI clock to minimum to keep it valid.
550 SPI1_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
552 /* Disable all irqs */
553 SPI1_IDR = 0xFFFFFFFF;
554 /* Set the vector. */
555 AIC_SVR(SPI1_ID) = spi1_irq_handler;
556 /* Initialize to edge triggered with defined priority. */
557 AIC_SMR(SPI1_ID) = AIC_SRCTYPE_INT_EDGE_TRIGGERED | SERIRQ_PRIORITY;
558 /* Enable the USART IRQ */
559 AIC_IECR = BV(SPI1_ID);
560 PMC_PCER = BV(SPI1_ID);
562 /* Enable interrupt on tx buffer empty */
563 SPI1_IER = BV(SPI_TXEMPTY);
566 SPI1_CR = BV(SPI_SPIEN);
574 static void spi1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
577 SPI1_CR = BV(SPI_SPIDIS);
579 /* Disable all irqs */
580 SPI1_IDR = 0xFFFFFFFF;
582 SER_SPI1_BUS_TXCLOSE;
584 /* Enable PIO on SPI pins */
585 PIOA_PER = BV(SPI1_SPCK) | BV(SPI1_MOSI) | BV(SPI1_MISO);
588 static void spi1_starttx(struct SerialHardware *_hw)
590 struct ArmSerial *hw = (struct ArmSerial *)_hw;
593 IRQ_SAVE_DISABLE(flags);
595 /* Send data only if the SPI is not already transmitting */
596 if (!hw->sending && !fifo_isempty(&ser_handles[SER_SPI1]->txfifo))
599 SPI1_TDR = fifo_pop(&ser_handles[SER_SPI1]->txfifo);
605 static void spi1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
607 SPI1_CSR0 &= ~SPI_SCBR;
609 ASSERT((uint8_t)DIV_ROUND(CPU_FREQ, rate));
610 SPI1_CSR0 |= DIV_ROUND(CPU_FREQ, rate) << SPI_SCBR_SHIFT;
614 static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
620 static bool tx_sending(struct SerialHardware* _hw)
622 struct ArmSerial *hw = (struct ArmSerial *)_hw;
626 // FIXME: move into compiler.h? Ditch?
628 #define C99INIT(name,val) .name = val
629 #elif defined(__GNUC__)
630 #define C99INIT(name,val) name: val
632 #warning No designated initializers, double check your code
633 #define C99INIT(name,val) (val)
637 * High-level interface data structures
639 static const struct SerialHardwareVT UART0_VT =
641 C99INIT(init, uart0_init),
642 C99INIT(cleanup, uart0_cleanup),
643 C99INIT(setBaudrate, uart0_setbaudrate),
644 C99INIT(setParity, uart0_setparity),
645 C99INIT(txStart, uart0_enabletxirq),
646 C99INIT(txSending, tx_sending),
649 static const struct SerialHardwareVT UART1_VT =
651 C99INIT(init, uart1_init),
652 C99INIT(cleanup, uart1_cleanup),
653 C99INIT(setBaudrate, uart1_setbaudrate),
654 C99INIT(setParity, uart1_setparity),
655 C99INIT(txStart, uart1_enabletxirq),
656 C99INIT(txSending, tx_sending),
659 static const struct SerialHardwareVT SPI0_VT =
661 C99INIT(init, spi0_init),
662 C99INIT(cleanup, spi0_cleanup),
663 C99INIT(setBaudrate, spi0_setbaudrate),
664 C99INIT(setParity, spi_setparity),
665 C99INIT(txStart, spi0_starttx),
666 C99INIT(txSending, tx_sending),
669 static const struct SerialHardwareVT SPI1_VT =
671 C99INIT(init, spi1_init),
672 C99INIT(cleanup, spi1_cleanup),
673 C99INIT(setBaudrate, spi1_setbaudrate),
674 C99INIT(setParity, spi_setparity),
675 C99INIT(txStart, spi1_starttx),
676 C99INIT(txSending, tx_sending),
680 static struct ArmSerial UARTDescs[SER_CNT] =
684 C99INIT(table, &UART0_VT),
685 C99INIT(txbuffer, uart0_txbuffer),
686 C99INIT(rxbuffer, uart0_rxbuffer),
687 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
688 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
690 C99INIT(sending, false),
694 C99INIT(table, &UART1_VT),
695 C99INIT(txbuffer, uart1_txbuffer),
696 C99INIT(rxbuffer, uart1_rxbuffer),
697 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
698 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
700 C99INIT(sending, false),
705 C99INIT(table, &SPI0_VT),
706 C99INIT(txbuffer, spi0_txbuffer),
707 C99INIT(rxbuffer, spi0_rxbuffer),
708 C99INIT(txbuffer_size, sizeof(spi0_txbuffer)),
709 C99INIT(rxbuffer_size, sizeof(spi0_rxbuffer)),
711 C99INIT(sending, false),
716 C99INIT(table, &SPI1_VT),
717 C99INIT(txbuffer, spi1_txbuffer),
718 C99INIT(rxbuffer, spi1_rxbuffer),
719 C99INIT(txbuffer_size, sizeof(spi1_txbuffer)),
720 C99INIT(rxbuffer_size, sizeof(spi1_rxbuffer)),
722 C99INIT(sending, false),
728 struct SerialHardware *ser_hw_getdesc(int unit)
730 ASSERT(unit < SER_CNT);
731 return &UARTDescs[unit].hw;
735 * Serial 0 TX interrupt handler
737 INLINE void uart0_irq_tx(void)
741 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART0]->txfifo;
743 if (fifo_isempty(txfifo))
746 * - Disable the TX empty interrupts
748 US0_IDR = BV(US_TXEMPTY);
750 UARTDescs[SER_UART0].sending = false;
754 char c = fifo_pop(txfifo);
755 SER_UART0_BUS_TXCHAR(c);
762 * Serial 0 RX complete interrupt handler.
764 INLINE void uart0_irq_rx(void)
768 /* Should be read before US_CRS */
769 ser_handles[SER_UART0]->status |= US0_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
770 US0_CR = BV(US_RSTSTA);
773 struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART0]->rxfifo;
775 if (fifo_isfull(rxfifo))
776 ser_handles[SER_UART0]->status |= SERRF_RXFIFOOVERRUN;
778 fifo_push(rxfifo, c);
784 * Serial IRQ dispatcher for USART0.
786 static DECLARE_ISR(uart0_irq_dispatcher)
788 if (US0_CSR & BV(US_RXRDY))
791 if (US0_CSR & BV(US_TXEMPTY))
794 /* Inform hw that we have served the IRQ */
799 * Serial 1 TX interrupt handler
801 INLINE void uart1_irq_tx(void)
805 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART1]->txfifo;
807 if (fifo_isempty(txfifo))
810 * - Disable the TX empty interrupts
812 US1_IDR = BV(US_TXEMPTY);
814 UARTDescs[SER_UART1].sending = false;
818 char c = fifo_pop(txfifo);
819 SER_UART1_BUS_TXCHAR(c);
826 * Serial 1 RX complete interrupt handler.
828 INLINE void uart1_irq_rx(void)
832 /* Should be read before US_CRS */
833 ser_handles[SER_UART1]->status |= US1_CSR & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
834 US1_CR = BV(US_RSTSTA);
837 struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART1]->rxfifo;
839 if (fifo_isfull(rxfifo))
840 ser_handles[SER_UART1]->status |= SERRF_RXFIFOOVERRUN;
842 fifo_push(rxfifo, c);
848 * Serial IRQ dispatcher for USART1.
850 static DECLARE_ISR(uart1_irq_dispatcher)
852 if (US1_CSR & BV(US_RXRDY))
855 if (US1_CSR & BV(US_TXEMPTY))
858 /* Inform hw that we have served the IRQ */
863 * SPI0 interrupt handler
865 static DECLARE_ISR(spi0_irq_handler)
870 /* Read incoming byte. */
871 if (!fifo_isfull(&ser_handles[SER_SPI0]->rxfifo))
872 fifo_push(&ser_handles[SER_SPI0]->rxfifo, c);
876 ser_handles[SER_SPI0]->status |= SERRF_RXFIFOOVERRUN;
880 if (!fifo_isempty(&ser_handles[SER_SPI0]->txfifo))
881 SPI0_TDR = fifo_pop(&ser_handles[SER_SPI0]->txfifo);
883 UARTDescs[SER_SPI0].sending = false;
885 /* Inform hw that we have served the IRQ */
893 * SPI1 interrupt handler
895 static DECLARE_ISR(spi1_irq_handler)
900 /* Read incoming byte. */
901 if (!fifo_isfull(&ser_handles[SER_SPI1]->rxfifo))
902 fifo_push(&ser_handles[SER_SPI1]->rxfifo, c);
906 ser_handles[SER_SPI1]->status |= SERRF_RXFIFOOVERRUN;
910 if (!fifo_isempty(&ser_handles[SER_SPI1]->txfifo))
911 SPI1_TDR = fifo_pop(&ser_handles[SER_SPI1]->txfifo);
913 UARTDescs[SER_SPI1].sending = false;
915 /* Inform hw that we have served the IRQ */