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14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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29 * Copyright 2008 Develer S.r.l. (http://www.develer.com/)
33 * \brief SPI driver with DMA.
35 * \author Francesco Sacchi <batt@develer.com>
36 * \author Luca Ottaviano <lottaviano@develer.com>
39 #include "cfg/cfg_spi_dma.h"
41 #include "spi_dma_at91.h"
42 #include "hw/hw_spi_dma.h"
45 #include <struct/fifobuf.h>
46 #include <struct/kfile_fifo.h>
47 #include <drv/timer.h>
50 #include <cpu/power.h>
52 #include <string.h> /* memset */
55 void spi_dma_setclock(uint32_t rate)
57 SPI0_CSR0 &= ~SPI_SCBR;
59 ASSERT((uint8_t)DIV_ROUND(CPU_FREQ, rate));
60 SPI0_CSR0 |= DIV_ROUND(CPU_FREQ, rate) << SPI_SCBR_SHIFT;
64 static int spi_dma_flush(UNUSED_ARG(struct KFile *, fd))
66 /* Wait for DMA to finish */
67 while (!(SPI0_SR & BV(SPI_TXBUFE)))
70 /* Wait until last bit has been shifted out */
71 while (!(SPI0_SR & BV(SPI_TXEMPTY)))
77 static size_t spi_dma_write(struct KFile *fd, const void *_buf, size_t size)
79 SPI0_PTCR = BV(PDC_TXTDIS);
80 SPI0_TPR = (reg32_t)_buf;
82 SPI0_PTCR = BV(PDC_TXTEN);
89 * Dummy buffer used to transmit 0xff chars while receiving data.
90 * This buffer is completetly constant and the compiler should allocate it
93 static const uint8_t tx_dummy_buf[CONFIG_SPI_DMA_MAX_RX] = { [0 ... (CONFIG_SPI_DMA_MAX_RX - 1)] = 0xFF };
95 static size_t spi_dma_read(UNUSED_ARG(struct KFile *, fd), void *_buf, size_t size)
97 size_t count, total_rx = 0;
98 uint8_t *buf = (uint8_t *)_buf;
102 count = MIN(size, (size_t)CONFIG_SPI_DMA_MAX_RX);
104 SPI0_PTCR = BV(PDC_TXTDIS) | BV(PDC_RXTDIS);
106 SPI0_RPR = (reg32_t)buf;
108 SPI0_TPR = (reg32_t)tx_dummy_buf;
111 /* Avoid reading the previous sent char */
115 SPI0_PTCR = BV(PDC_RXTEN) | BV(PDC_TXTEN);
117 /* wait for transfer to finish */
118 while (!(SPI0_SR & BV(SPI_ENDRX)))
125 SPI0_PTCR = BV(PDC_RXTDIS) | BV(PDC_TXTDIS);
130 #define SPI_DMA_IRQ_PRIORITY 4
132 void spi_dma_init(SpiDmaAt91 *spi)
134 /* Disable PIO on SPI pins */
135 PIOA_PDR = BV(SPI0_SPCK) | BV(SPI0_MOSI) | BV(SPI0_MISO);
138 SPI0_CR = BV(SPI_SWRST);
141 * Set SPI to master mode, fixed peripheral select, chip select directly connected to a peripheral device,
142 * SPI clock set to MCK, mode fault detection disabled, loopback disable, NPCS0 active, Delay between CS = 0
144 SPI0_MR = BV(SPI_MSTR) | BV(SPI_MODFDIS);
148 * At reset clock division factor is set to 0, that is
149 * *forbidden*. Set SPI clock to minimum to keep it valid.
151 SPI0_CSR0 = BV(SPI_NCPHA) | (255 << SPI_SCBR_SHIFT);
153 /* Disable all irqs */
154 SPI0_IDR = 0xFFFFFFFF;
155 /* Enable SPI clock. */
156 PMC_PCER = BV(SPI0_ID);
159 SPI0_CR = BV(SPI_SPIEN);
161 DB(spi->fd._type = KFT_SPIDMAAT91);
162 spi->fd.write = spi_dma_write;
163 spi->fd.read = spi_dma_read;
164 spi->fd.flush = spi_dma_flush;
166 SPI_DMA_STROBE_INIT();