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29 * Copyright 2008 Develer S.r.l. (http://www.develer.com/)
30 * All Rights Reserved.
33 * \brief Stepper driver interface implementation.
35 * This module use the three timer on the at91 family, to generate a
36 * six periodic variable pwm waveform. The pulse width is fix, and could
37 * change by setting the STEPPER_DELAY_ON_COMPARE_C define, but you make
38 * an attention to do this, becouse the pulse width is not exactly
39 * STEPPER_DELAY_ON_COMPARE_C. The pulse width depend also to latency
40 * time of cpu to serve an interrupt, this generate an pwm waveform affect
41 * to noise. This noise not effect the period but only the pulse width,
42 * becouse the raising edge is generate by hardware comply with the our
45 * Note: is most important to set STEPPER_DELAY_ON_COMPARE_C value minor
46 * than a interrupt time service, becouse the falling edge must be happen
47 * inside to inerrupt service to guarantee a correct functionaly of pwm
52 * \author Daniele Basile <asterix@develer.com>
55 #include "stepper_at91.h"
57 #include "cfg/cfg_stepper.h"
58 #include <cfg/macros.h>
59 #include <cfg/debug.h>
61 #include <cpu/types.h>
68 * Delay to set C compare to clear output
69 * on select TIO output
71 #define STEPPER_DELAY_ON_COMPARE_C 20
74 * Forward declaration for interrupt handler
76 static ISR_PROTO(stepper_tc0_irq);
77 static ISR_PROTO(stepper_tc1_irq);
78 static ISR_PROTO(stepper_tc2_irq);
80 ///< Static array of timer counter struct for stepper.
81 static struct TimerCounter stepper_timers[CONFIG_TC_STEPPER_MAX_NUM] =
83 { //Timer Counter settings for TIOA0 output pin
85 .blk_ctrl_set = TC_NONEXC0,
86 .chl_mode_reg = &TC0_CMR,
87 .chl_ctrl_reg = &TC0_CCR,
88 .comp_effect_mask = TC_ACPA_MASK,
89 .comp_effect_set = TC_ACPA_SET_OUTPUT,
90 .comp_effect_clear = TC_ACPA_CLEAR_OUTPUT,
91 .comp_effect_c_mask = TC_ACPC_MASK,
92 .comp_effect_c_clear = TC_ACPC_CLEAR_OUTPUT,
93 .ext_event_set = TC_EEVT_XC0,
95 .comp_c_reg = &TC0_RC,
96 .count_val_reg = &TC0_CV,
97 .irq_enable_reg = &TC0_IER,
98 .irq_disable_reg = &TC0_IDR,
99 .irq_set_mask = BV(TC_CPAS),
100 .irq_mask_reg = &TC0_IMR,
101 .isr = stepper_tc0_irq,
102 .status_reg = &TC0_SR,
107 { //Timer Counter settings for TIOB0 output pin
109 .blk_ctrl_set = TC_NONEXC0,
110 .chl_mode_reg = &TC0_CMR,
111 .chl_ctrl_reg = &TC0_CCR,
113 .comp_c_reg = &TC0_RC,
114 .count_val_reg = &TC0_CV,
115 .comp_effect_mask = TC_BCPB_MASK,
116 .comp_effect_set = TC_BCPB_SET_OUTPUT,
117 .comp_effect_clear = TC_BCPB_CLEAR_OUTPUT,
118 .comp_effect_c_mask = TC_BCPC_MASK,
119 .comp_effect_c_clear = TC_BCPC_CLEAR_OUTPUT,
120 .ext_event_set = TC_EEVT_XC0,
121 .irq_enable_reg = &TC0_IER,
122 .irq_disable_reg = &TC0_IDR,
123 .irq_set_mask = BV(TC_CPBS),
124 .irq_mask_reg = &TC0_IMR,
125 .isr = stepper_tc0_irq,
126 .status_reg = &TC0_SR,
131 { //Timer Counter settings for TIOA1 output pin
133 .blk_ctrl_set = TC_NONEXC1,
134 .chl_mode_reg = &TC1_CMR,
135 .chl_ctrl_reg = &TC1_CCR,
137 .comp_c_reg = &TC1_RC,
138 .count_val_reg = &TC1_CV,
139 .comp_effect_mask = TC_ACPA_MASK,
140 .comp_effect_set = TC_ACPA_SET_OUTPUT,
141 .comp_effect_clear = TC_ACPA_CLEAR_OUTPUT,
142 .comp_effect_c_mask = TC_ACPC_MASK,
143 .comp_effect_c_clear = TC_ACPC_CLEAR_OUTPUT,
144 .ext_event_set = TC_EEVT_XC1,
145 .irq_enable_reg = &TC1_IER,
146 .irq_disable_reg = &TC1_IDR,
147 .irq_set_mask = BV(TC_CPAS),
148 .irq_mask_reg = &TC1_IMR,
149 .isr = stepper_tc1_irq,
150 .status_reg = &TC1_SR,
155 { //Timer Counter settings for TIOB1 output pin
157 .blk_ctrl_set = TC_NONEXC1,
158 .chl_mode_reg = &TC1_CMR,
159 .chl_ctrl_reg = &TC1_CCR,
161 .comp_c_reg = &TC1_RC,
162 .count_val_reg = &TC1_CV,
163 .comp_effect_mask = TC_BCPB_MASK,
164 .comp_effect_set = TC_BCPB_SET_OUTPUT,
165 .comp_effect_clear = TC_BCPB_CLEAR_OUTPUT,
166 .comp_effect_c_mask = TC_BCPC_MASK,
167 .comp_effect_c_clear = TC_BCPC_CLEAR_OUTPUT,
168 .ext_event_set = TC_EEVT_XC1,
169 .irq_enable_reg = &TC1_IER,
170 .irq_disable_reg = &TC1_IDR,
171 .irq_set_mask = BV(TC_CPBS),
172 .irq_mask_reg = &TC1_IMR,
173 .isr = stepper_tc1_irq,
174 .status_reg = &TC1_SR,
179 { //Timer Counter settings for TIOA2 output pin
181 .blk_ctrl_set = TC_NONEXC2,
182 .chl_mode_reg = &TC2_CMR,
183 .chl_ctrl_reg = &TC2_CCR,
185 .comp_c_reg = &TC2_RC,
186 .count_val_reg = &TC2_CV,
187 .comp_effect_mask = TC_ACPA_MASK,
188 .comp_effect_set = TC_ACPA_SET_OUTPUT,
189 .comp_effect_clear = TC_ACPA_CLEAR_OUTPUT,
190 .comp_effect_c_mask = TC_ACPC_MASK,
191 .comp_effect_c_clear = TC_ACPC_CLEAR_OUTPUT,
192 .ext_event_set = TC_EEVT_XC2,
193 .irq_enable_reg = &TC2_IER,
194 .irq_disable_reg = &TC2_IDR,
195 .irq_set_mask = BV(TC_CPAS),
196 .irq_mask_reg = &TC2_IMR,
197 .isr = stepper_tc2_irq,
198 .status_reg = &TC2_SR,
203 { //Timer Counter settings for TIOB2 output pin
205 .blk_ctrl_set = TC_NONEXC2,
206 .chl_mode_reg = &TC2_CMR,
207 .chl_ctrl_reg = &TC2_CCR,
209 .comp_c_reg = &TC2_RC,
210 .count_val_reg = &TC2_CV,
211 .comp_effect_mask = TC_BCPB_MASK,
212 .comp_effect_set = TC_BCPB_SET_OUTPUT,
213 .comp_effect_clear = TC_BCPB_CLEAR_OUTPUT,
214 .comp_effect_c_mask = TC_BCPC_MASK,
215 .comp_effect_c_clear = TC_BCPC_CLEAR_OUTPUT,
216 .ext_event_set = TC_EEVT_XC2,
217 .irq_enable_reg = &TC2_IER,
218 .irq_disable_reg = &TC2_IDR,
219 .irq_set_mask = BV(TC_CPBS),
220 .irq_mask_reg = &TC2_IMR,
221 .isr = stepper_tc2_irq,
222 .status_reg = &TC2_SR,
230 * Generic TIO interrupt handler.
232 INLINE void stepper_tc_tio_irq(struct TimerCounter * t)
235 *t->chl_mode_reg &= ~t->comp_effect_c_mask;
236 *t->chl_mode_reg |= t->comp_effect_c_clear;
239 * Cleat TIO output on c register compare.
240 * This generate an pulse with variable lenght, this
241 * depend to delay that interrupt is realy service.
243 *t->comp_c_reg = *t->count_val_reg + STEPPER_DELAY_ON_COMPARE_C;
245 //Call the associate callback
246 t->callback(t->motor);
248 *t->chl_mode_reg &= ~t->comp_effect_c_mask;
253 * Interrupt handler for timer counter TCKL0
255 DECLARE_ISR(stepper_tc0_irq)
258 * Warning: when we read the status_reg register, we reset it.
259 * That mean if is occur an interrupt event we can read only
260 * the last that has been occur. To not miss an interrupt event
261 * we save the status_reg register and then we read it.
263 uint32_t status_reg = TC0_SR & TC0_IMR;
265 if (status_reg & BV(TC_CPAS))
266 stepper_tc_tio_irq(&stepper_timers[TC_TIOA0]);
268 if (status_reg & BV(TC_CPBS))
269 stepper_tc_tio_irq(&stepper_timers[TC_TIOB0]);
271 /* Inform hw that we have served the IRQ */
277 * Interrupt handler for timer counter TCKL1
279 DECLARE_ISR(stepper_tc1_irq)
282 * Warning: when we read the status_reg register, we reset it.
283 * That mean if is occur an interrupt event we can read only
284 * the last that has been occur. To not miss an interrupt event
285 * we save the status_reg register and then we read it.
287 uint32_t status_reg = TC1_SR & TC1_IMR;
289 if (status_reg & BV(TC_CPAS))
290 stepper_tc_tio_irq(&stepper_timers[TC_TIOA1]);
292 if (status_reg & BV(TC_CPBS))
293 stepper_tc_tio_irq(&stepper_timers[TC_TIOB1]);
296 /* Inform hw that we have served the IRQ */
302 * Interrupt handler for timer counter TCKL2
304 DECLARE_ISR(stepper_tc2_irq)
308 * Warning: when we read the status_reg register, we reset it.
309 * That mean if is occur an interrupt event we can read only
310 * the last that has been occur. To not miss an interrupt event
311 * we save the status_reg register and then we read it.
313 uint32_t status_reg = TC2_SR & TC2_IMR;
315 if (status_reg & BV(TC_CPAS))
316 stepper_tc_tio_irq(&stepper_timers[TC_TIOA2]);
318 if (status_reg & BV(TC_CPBS))
319 stepper_tc_tio_irq(&stepper_timers[TC_TIOB2]);
321 /* Inform hw that we have served the IRQ */
327 * Timer couter setup.
329 * This function apply to select timer couter all needed settings.
330 * Every settings are stored in stepper_timers[].
332 void stepper_tc_setup(int index, stepper_isr_t callback, struct Stepper *motor)
334 ASSERT(index < CONFIG_TC_STEPPER_MAX_NUM);
336 motor->timer = &stepper_timers[index];
338 //Disable PIO controller and enable TIO function
339 TIO_PIO_PDR = BV(motor->timer->tio_pin);
340 TIO_PIO_ABSR = BV(motor->timer->tio_pin);
343 * Sets timer counter in waveform mode.
345 * - Waveform mode 00 (see datasheet for more detail.)
346 * - Master clock prescaler to STEPPER_MCK_PRESCALER
347 * - Set none external event
348 * - Clear pin output on comp_reg
349 * - None effect on reg C compare
351 *motor->timer->chl_mode_reg = BV(TC_WAVE);
352 *motor->timer->chl_mode_reg |= motor->timer->ext_event_set;
353 *motor->timer->chl_mode_reg &= ~TC_WAVSEL_MASK;
354 *motor->timer->chl_mode_reg |= TC_WAVSEL_UP;
355 *motor->timer->chl_mode_reg |= STEPPER_MCK_PRESCALER;
356 *motor->timer->chl_mode_reg |= motor->timer->comp_effect_clear;
357 *motor->timer->chl_mode_reg &= ~motor->timer->comp_effect_c_mask;
359 //Reset comp_reg and C compare register
360 *motor->timer->comp_reg = 0;
361 *motor->timer->comp_c_reg = 0;
363 //Register interrupt vector
365 IRQ_SAVE_DISABLE(flags);
368 * Warning: To guarantee a correct management of interrupt event, we must
369 * trig the interrupt on level sensitive. This becouse, we have only a common
370 * line for interrupt request, and if we have at the same time two interrupt
371 * request could be that the is service normaly but the second will never
372 * been detected and interrupt will stay active but never serviced.
374 AIC_SVR(motor->timer->timer_id) = motor->timer->isr;
375 AIC_SMR(motor->timer->timer_id) = AIC_SRCTYPE_INT_LEVEL_SENSITIVE;
376 AIC_IECR = BV(motor->timer->timer_id);
378 // Disable interrupt on select timer counter
379 stepper_tc_irq_disable(motor->timer);
384 motor->timer->callback = callback;
385 motor->timer->motor = motor;
389 * Timer counter init.
391 void stepper_tc_init(void)
395 ASSERT(CONFIG_NUM_STEPPER_MOTORS <= CONFIG_TC_STEPPER_MAX_NUM);
398 * Enable timer counter:
399 * - power on all timer counter
400 * - disable all interrupt
401 * - disable all external event/timer source
403 for (int i = 0; i < CONFIG_TC_STEPPER_MAX_NUM; i++)
405 PMC_PCER = BV(stepper_timers[i].timer_id);
406 *stepper_timers[i].irq_disable_reg = 0xFFFFFFFF;
407 TC_BMR = stepper_timers[i].blk_ctrl_set;
411 * Enable timer counter and start it.
413 for (int i = 0; i < CONFIG_TC_STEPPER_MAX_NUM; i++)
414 *stepper_timers[i].chl_ctrl_reg = (BV(TC_CLKEN) | BV(TC_SWTRG));