1 /****************************************************************************
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2 * Copyright (c) 2006 by Michael Fischer. All rights reserved.
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4 * Redistribution and use in source and binary forms, with or without
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5 * modification, are permitted provided that the following conditions
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8 * 1. Redistributions of source code must retain the above copyright
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9 * notice, this list of conditions and the following disclaimer.
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10 * 2. Redistributions in binary form must reproduce the above copyright
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11 * notice, this list of conditions and the following disclaimer in the
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12 * documentation and/or other materials provided with the distribution.
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13 * 3. Neither the name of the author nor the names of its contributors may
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14 * be used to endorse or promote products derived from this software
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15 * without specific prior written permission.
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17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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20 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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21 * THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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23 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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24 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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25 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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26 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
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27 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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30 ****************************************************************************
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34 * 18.12.06 mifi First Version
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35 * The hardware initialization is based on the startup file
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36 * crtat91sam7x256_rom.S from NutOS 4.2.1.
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37 * Therefore partial copyright by egnite Software GmbH.
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38 ****************************************************************************/
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41 * Some defines for the program status registers
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43 ARM_MODE_USER = 0x10 /* Normal User Mode */
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44 ARM_MODE_FIQ = 0x11 /* FIQ Fast Interrupts Mode */
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45 ARM_MODE_IRQ = 0x12 /* IRQ Standard Interrupts Mode */
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46 ARM_MODE_SVC = 0x13 /* Supervisor Interrupts Mode */
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47 ARM_MODE_ABORT = 0x17 /* Abort Processing memory Faults Mode */
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48 ARM_MODE_UNDEF = 0x1B /* Undefined Instructions Mode */
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49 ARM_MODE_SYS = 0x1F /* System Running in Priviledged Operating Mode */
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50 ARM_MODE_MASK = 0x1F
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52 I_BIT = 0x80 /* disable IRQ when I bit is set */
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53 F_BIT = 0x40 /* disable IRQ when I bit is set */
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56 * Register Base Address
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58 AIC_BASE = 0xFFFFF000
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59 AIC_EOICR_OFF = 0x130
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60 AIC_IDCR_OFF = 0x124
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62 RSTC_MR = 0xFFFFFD08
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63 RSTC_KEY = 0xA5000000
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64 RSTC_URSTEN = 0x00000001
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66 WDT_BASE = 0xFFFFFD40
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67 WDT_MR_OFF = 0x00000004
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68 WDT_WDDIS = 0x00008000
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70 MC_BASE = 0xFFFFFF00
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71 MC_FMR_OFF = 0x00000060
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72 MC_FWS_1FWS = 0x00480100
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74 .section .vectors,"ax"
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77 /****************************************************************************/
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78 /* Vector table and reset entry */
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79 /****************************************************************************/
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81 ldr pc, ResetAddr /* Reset */
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82 ldr pc, UndefAddr /* Undefined instruction */
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83 ldr pc, SWIAddr /* Software interrupt */
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84 ldr pc, PAbortAddr /* Prefetch abort */
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85 ldr pc, DAbortAddr /* Data abort */
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86 ldr pc, ReservedAddr /* Reserved */
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87 ldr pc, [pc, #-0xF20] /* IRQ interrupt */
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88 ldr pc, FIQAddr /* FIQ interrupt */
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92 ResetAddr: .word ResetHandler
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93 UndefAddr: .word UndefHandler
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94 SWIAddr: .word SWIHandler
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95 PAbortAddr: .word PAbortHandler
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96 DAbortAddr: .word DAbortHandler
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97 ReservedAddr: .word 0
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98 IRQAddr: .word IRQHandler
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99 FIQAddr: .word FIQHandler
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103 .section .init, "ax"
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106 .global ResetHandler
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107 .global ExitFunction
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109 /****************************************************************************/
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110 /* Reset handler */
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111 /****************************************************************************/
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114 * The watchdog is enabled after processor reset. Disable it.
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118 str r0, [r1, #WDT_MR_OFF]
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122 * Enable user reset: assertion length programmed to 1ms
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124 ldr r0, =(RSTC_KEY | RSTC_URSTEN | (4 << 8))
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130 * Use 2 cycles for flash access.
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133 ldr r0, =MC_FWS_1FWS
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134 str r0, [r1, #MC_FMR_OFF]
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138 * Disable all interrupts. Useful for debugging w/o target reset.
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142 str r0, [r1, #AIC_EOICR_OFF]
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143 str r0, [r1, #AIC_IDCR_OFF]
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147 * Setup a stack for each mode
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149 msr CPSR_c, #ARM_MODE_UNDEF | I_BIT | F_BIT /* Undefined Instruction Mode */
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150 ldr sp, =__stack_und_end
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152 msr CPSR_c, #ARM_MODE_ABORT | I_BIT | F_BIT /* Abort Mode */
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153 ldr sp, =__stack_abt_end
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155 msr CPSR_c, #ARM_MODE_FIQ | I_BIT | F_BIT /* FIQ Mode */
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156 ldr sp, =__stack_fiq_end
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158 msr CPSR_c, #ARM_MODE_IRQ | I_BIT | F_BIT /* IRQ Mode */
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159 ldr sp, =__stack_irq_end
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161 msr CPSR_c, #ARM_MODE_SVC | I_BIT | F_BIT /* Supervisor Mode */
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162 ldr sp, =__stack_svc_end
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166 * Clear .bss section
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168 ldr r1, =__bss_start
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173 strne r3, [r1], #+4
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181 mov r0, #0 /* No arguments */
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182 mov r1, #0 /* No arguments */
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185 bx r2 /* And jump... */
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194 /****************************************************************************/
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195 /* Default interrupt handler */
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196 /****************************************************************************/
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217 .weak UndefHandler, PAbortHandler, DAbortHandler
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218 .weak IRQHandler, FIQHandler
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