4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
34 * \author Francesco Sacchi <batt@develer.com>
36 * \brief AT91SAM7S256 CRT, adapted from NUt/OS, see license below.
40 * Copyright (C) 2005-2007 by egnite Software GmbH. All rights reserved.
42 * Redistribution and use in source and binary forms, with or without
43 * modification, are permitted provided that the following conditions
46 * 1. Redistributions of source code must retain the above copyright
47 * notice, this list of conditions and the following disclaimer.
48 * 2. Redistributions in binary form must reproduce the above copyright
49 * notice, this list of conditions and the following disclaimer in the
50 * documentation and/or other materials provided with the distribution.
51 * 3. Neither the name of the copyright holders nor the names of
52 * contributors may be used to endorse or promote products derived
53 * from this software without specific prior written permission.
55 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
57 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
58 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
59 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
61 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
62 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
63 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
65 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
68 * For additional information see http://www.ethernut.de/
72 #include <cpu/detect.h>
73 #include "cfg/cfg_arch.h"
76 #if CPU_FREQ != 48023000L
77 /* Avoid errors on nightly test */
78 #if !defined(ARCH_NIGHTTEST) || !(ARCH & ARCH_NIGHTTEST)
79 #warning Clock registers set for 48.023MHz operation, revise following code if you want a different clock.
84 #if CPU_ARM_SAM7S_LARGE || CPU_ARM_SAM7X
86 * With a 18.420MHz cristal, master clock is:
87 * (((18.420 * PLL_MUL_VAL + 1) / PLL_DIV_VAL) / AT91MCK_PRES) = 48.023MHz
89 #define PLL_MUL_VAL 72 /**< Real multiplier value is PLL_MUL_VAL + 1! */
90 #define PLL_DIV_VAL 14
91 #define AT91MCK_PRES PMC_PRES_CLK_2
94 * Register I/O adresses.
96 #define MC_BASE 0xFFFFFF00
97 #define MC_FMR_OFF 0x00000060
98 #define MC_FWS_2R3W 0x00000100
100 #define AIC_BASE 0xFFFFF000
101 #define AIC_EOICR_OFF 0x00000130
102 #define AIC_IDCR_OFF 0x00000124
104 #define WDT_BASE 0xFFFFFD40
105 #define WDT_MR_OFF 0x00000004
106 #define WDT_WDDIS (1 << 15)
108 #define PMC_BASE 0xFFFFFC00
109 #define PMC_PCER_OFF 0x00000010
110 #define PMC_SR_OFF 0x00000068
111 #define PMC_MCKR_OFF 0x00000030
112 #define PMC_MOSCS (1 << 0)
113 #define PMC_LOCK (1 << 2)
114 #define PMC_MCKRDY (1 << 3)
115 #define PMC_CSS_MASK 0x00000003
116 #define PMC_CSS_PLL_CLK 0x00000003
117 #define PMC_PRES_MASK 0x0000001C
118 #define PMC_PRES_CLK_2 0x00000004
120 #if CPU_ARM_SAM7S_LARGE
121 #define PMC_PIO_CLK_EN (1 << 2)
123 #define PMC_PIO_CLK_EN ((1 << 2) | (1 << 3))
125 #error CPU not supported
128 #define CKGR_MOR_OFF 0x00000020
129 #define CKGR_PLLR_OFF 0x0000002C
130 #define CKGR_MOSCEN (1 << 0)
131 #define CKGR_MUL_SHIFT 16
132 #define CKGR_PLLCOUNT_SHIFT 8
134 #define RSTC_MR 0xFFFFFD08
135 #define RSTC_KEY 0xA5000000
136 #define RSTC_URSTEN (1 << 0)
138 #define ARM_MODE_USR 0x10
139 #define ARM_MODE_FIQ 0x11
140 #define ARM_MODE_IRQ 0x12
141 #define ARM_MODE_SVC 0x13
142 #define ARM_MODE_ABORT 0x17
143 #define ARM_MODE_UNDEF 0x1B
144 #define ARM_MODE_SYS 0x1F
147 #error No register I/O definition for selected ARM CPU
152 * Section 0: Vector table and reset entry.
154 .section .vectors,"ax",%progbits
158 ldr pc, [pc, #24] /* Reset */
159 ldr pc, [pc, #24] /* Undefined instruction */
160 ldr pc, [pc, #24] /* Software interrupt */
161 ldr pc, [pc, #24] /* Prefetch abort */
162 ldr pc, [pc, #24] /* Data abort */
163 ldr pc, [pc, #24] /* Reserved */
166 * On IRQ the PC will be loaded from AIC_IVR, which
167 * provides the address previously set in AIC_SVR.
168 * The interrupt routine will be called in ARM_MODE_IRQ
169 * with IRQ disabled and FIQ unchanged.
171 ldr pc, [pc, #-0xF20] /* Interrupt request, auto vectoring. */
172 ldr pc, [pc, #-0xF20] /* Fast interrupt request, auto vectoring. */
177 .word __prefetch_abort
181 .set __undef, __xcpt_dummy_undef
183 .set __swi, __xcpt_dummy_swi
184 .weak __prefetch_abort
185 .set __prefetch_abort, __xcpt_dummy_pref
187 .set __data_abort, __xcpt_dummy_dab
189 /** .global __xcpt_dummy*/
205 * Hardware initialization.
207 .section .init, "ax", %progbits
211 * Use 2 cycles for flash access.
215 str r0, [r1, #MC_FMR_OFF]
218 * Disable all interrupts. Useful for debugging w/o target reset.
222 str r0, [r1, #AIC_EOICR_OFF]
223 str r0, [r1, #AIC_IDCR_OFF]
226 * The watchdog is enabled after processor reset. Disable it.
230 str r0, [r1, #WDT_MR_OFF]
233 * Enable the main oscillator. Set startup time of 6 * 8 slow
234 * clock cycles and wait until oscillator is stabilized.
238 orr r0, r0, #CKGR_MOSCEN
239 str r0, [r1, #CKGR_MOR_OFF]
241 ldr r0, [r1, #PMC_SR_OFF]
246 * Switch to Slow oscillator clock.
248 ldr r0, [r1, #PMC_MCKR_OFF]
249 and r0, r0, #~PMC_CSS_MASK
250 str r0, [r1, #PMC_MCKR_OFF]
252 ldr r0, [r1, #PMC_SR_OFF]
257 * Switch to prescaler div 1 factor.
259 ldr r0, [r1, #PMC_MCKR_OFF]
260 and r0, r0, #~PMC_PRES_MASK
261 str r0, [r1, #PMC_MCKR_OFF]
263 ldr r0, [r1, #PMC_SR_OFF]
269 * PLLfreq = crystal / divider * (multiplier + 1)
270 * Wait 28 clock cycles until PLL is locked.
272 ldr r0, =((PLL_MUL_VAL << CKGR_MUL_SHIFT) | (28 << CKGR_PLLCOUNT_SHIFT) | PLL_DIV_VAL)
274 str r0, [r1, #CKGR_PLLR_OFF]
276 ldr r0, [r1, #PMC_SR_OFF]
281 * Set master clock prescaler.
283 mov r0, #AT91MCK_PRES
284 str r0, [r1, #PMC_MCKR_OFF]
286 ldr r0, [r1, #PMC_SR_OFF]
291 * Switch to PLL clock. Trying to set this together with the
292 * prescaler fails (see datasheets).
294 ldr r0, [r1, #PMC_MCKR_OFF]
295 orr r0, r0, #PMC_CSS_PLL_CLK
296 str r0, [r1, #PMC_MCKR_OFF]
298 ldr r0, [r1, #PMC_SR_OFF]
303 * Enable external reset key.
305 ldr r0, =(RSTC_KEY | RSTC_URSTEN)
310 * Set exception stack pointers
312 ldr r0, =__stack_fiq_end
313 msr CPSR_c, #ARM_MODE_FIQ | 0xC0
315 ldr r0, =__stack_irq_end
316 msr CPSR_c, #ARM_MODE_IRQ | 0xC0
318 ldr r0, =__stack_abt_end
319 msr CPSR_c, #ARM_MODE_ABORT | 0xC0
321 ldr r0, =__stack_und_end
322 msr CPSR_c, #ARM_MODE_UNDEF | 0xC0
324 ldr r0, =__stack_svc_end
325 msr CPSR_c, #ARM_MODE_SVC | 0xC0
341 * Relocate .data section (Copy from ROM to RAM).
344 ldr r2, =__data_start
354 * Initialize user stack pointer.
356 /* msr CPSR_c, #ARM_MODE_SYS | 0xC0 */
357 ldr r13, =__stack_end
361 * Enable clock for PIO(s)
364 mov r0, #PMC_PIO_CLK_EN
365 str r0, [r1, #PMC_PCER_OFF]