4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
35 * \author Francesco Sacchi <batt@develer.com>
37 * \brief AT91SAM7S256 CRT, adapted from NUt/OS, see license below.
41 * Copyright (C) 2005-2007 by egnite Software GmbH. All rights reserved.
43 * Redistribution and use in source and binary forms, with or without
44 * modification, are permitted provided that the following conditions
47 * 1. Redistributions of source code must retain the above copyright
48 * notice, this list of conditions and the following disclaimer.
49 * 2. Redistributions in binary form must reproduce the above copyright
50 * notice, this list of conditions and the following disclaimer in the
51 * documentation and/or other materials provided with the distribution.
52 * 3. Neither the name of the copyright holders nor the names of
53 * contributors may be used to endorse or promote products derived
54 * from this software without specific prior written permission.
56 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
58 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
59 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
60 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
62 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
63 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
64 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
65 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
66 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69 * For additional information see http://www.ethernut.de/
73 #include <cpu/detect.h>
74 #include "cfg/cfg_arch.h"
77 #if CPU_FREQ != 48023000L
78 /* Avoid errors on nightly test */
79 #if !defined(ARCH_NIGHTTEST) || !(ARCH & ARCH_NIGHTTEST)
80 #warning Clock registers set for 48.023MHz operation, revise following code if you want a different clock.
85 #if CPU_ARM_SAM7S_LARGE || CPU_ARM_SAM7X
87 * With a 18.420MHz cristal, master clock is:
88 * (((18.420 * PLL_MUL_VAL + 1) / PLL_DIV_VAL) / AT91MCK_PRES) = 48.023MHz
90 #define PLL_MUL_VAL 72 /**< Real multiplier value is PLL_MUL_VAL + 1! */
91 #define PLL_DIV_VAL 14
92 #define AT91MCK_PRES PMC_PRES_CLK_2
95 * Register I/O adresses.
98 #define MC_BASE 0xFFFFFF00
99 #define MC_FMR_OFF 0x00000060
100 #define MC_FWS_2R3W 0x00000100
102 #define AIC_BASE 0xFFFFF000
103 #define AIC_EOICR_OFF 0x00000130
104 #define AIC_IDCR_OFF 0x00000124
106 #define WDT_BASE 0xFFFFFD40
107 #define WDT_MR_OFF 0x00000004
108 #define WDT_WDDIS (1 << 15)
110 #define PMC_BASE 0xFFFFFC00
111 #define PMC_SR_OFF 0x00000068
112 #define PMC_MCKR_OFF 0x00000030
113 #define PMC_MOSCS (1 << 0)
114 #define PMC_LOCK (1 << 2)
115 #define PMC_MCKRDY (1 << 3)
116 #define PMC_CSS_MASK 0x00000003
117 #define PMC_CSS_PLL_CLK 0x00000003
118 #define PMC_PRES_MASK 0x0000001C
119 #define PMC_PRES_CLK_2 0x00000004
121 #define CKGR_MOR_OFF 0x00000020
122 #define CKGR_PLLR_OFF 0x0000002C
123 #define CKGR_MOSCEN (1 << 0)
124 #define CKGR_MUL_SHIFT 16
125 #define CKGR_PLLCOUNT_SHIFT 8
127 #define RSTC_MR 0xFFFFFD08
128 #define RSTC_KEY 0xA5000000
129 #define RSTC_URSTEN (1 << 0)
131 #define ARM_MODE_FIQ 0x11
132 #define ARM_MODE_IRQ 0x12
133 #define ARM_MODE_SVC 0x13
134 #define ARM_MODE_ABORT 0x17
135 #define ARM_MODE_UNDEF 0x1B
138 #error No register I/O definition for selected ARM CPU
143 * Section 0: Vector table and reset entry.
145 .section .vectors,"ax",%progbits
149 ldr pc, [pc, #24] /* Reset */
150 ldr pc, [pc, #24] /* Undefined instruction */
151 ldr pc, [pc, #24] /* Software interrupt */
152 ldr pc, [pc, #24] /* Prefetch abort */
153 ldr pc, [pc, #24] /* Data abort */
154 ldr pc, [pc, #24] /* Reserved */
157 * On IRQ the PC will be loaded from AIC_IVR, which
158 * provides the address previously set in AIC_SVR.
159 * The interrupt routine will be called in ARM_MODE_IRQ
160 * with IRQ disabled and FIQ unchanged.
162 ldr pc, [pc, #-0xF20] /* Interrupt request, auto vectoring. */
163 ldr pc, [pc, #-0xF20] /* Fast interrupt request, auto vectoring. */
168 .word __prefetch_abort
172 .set __undef, __xcpt_dummy_undef
174 .set __swi, __xcpt_dummy_swi
175 .weak __prefetch_abort
176 .set __prefetch_abort, __xcpt_dummy_pref
178 .set __data_abort, __xcpt_dummy_dab
180 /** .global __xcpt_dummy*/
196 * Hardware initialization.
198 .section .init, "ax", %progbits
202 * Use 2 cycles for flash access.
206 str r0, [r1, #MC_FMR_OFF]
209 * Disable all interrupts. Useful for debugging w/o target reset.
213 str r0, [r1, #AIC_EOICR_OFF]
214 str r0, [r1, #AIC_IDCR_OFF]
217 * The watchdog is enabled after processor reset. Disable it.
221 str r0, [r1, #WDT_MR_OFF]
224 * Enable the main oscillator. Set startup time of 6 * 8 slow
225 * clock cycles and wait until oscillator is stabilized.
229 orr r0, r0, #CKGR_MOSCEN
230 str r0, [r1, #CKGR_MOR_OFF]
232 ldr r0, [r1, #PMC_SR_OFF]
237 * Switch to Slow oscillator clock.
239 ldr r0, [r1, #PMC_MCKR_OFF]
240 and r0, r0, #~PMC_CSS_MASK
241 str r0, [r1, #PMC_MCKR_OFF]
243 ldr r0, [r1, #PMC_SR_OFF]
248 * Switch to prescaler div 1 factor.
250 ldr r0, [r1, #PMC_MCKR_OFF]
251 and r0, r0, #~PMC_PRES_MASK
252 str r0, [r1, #PMC_MCKR_OFF]
254 ldr r0, [r1, #PMC_SR_OFF]
260 * PLLfreq = crystal / divider * (multiplier + 1)
261 * Wait 28 clock cycles until PLL is locked.
263 ldr r0, =((PLL_MUL_VAL << CKGR_MUL_SHIFT) | (28 << CKGR_PLLCOUNT_SHIFT) | PLL_DIV_VAL)
265 str r0, [r1, #CKGR_PLLR_OFF]
267 ldr r0, [r1, #PMC_SR_OFF]
272 * Set master clock prescaler.
274 mov r0, #AT91MCK_PRES
275 str r0, [r1, #PMC_MCKR_OFF]
277 ldr r0, [r1, #PMC_SR_OFF]
282 * Switch to PLL clock. Trying to set this together with the
283 * prescaler fails (see datasheets).
285 ldr r0, [r1, #PMC_MCKR_OFF]
286 orr r0, r0, #PMC_CSS_PLL_CLK
287 str r0, [r1, #PMC_MCKR_OFF]
289 ldr r0, [r1, #PMC_SR_OFF]
294 * Enable external reset key.
296 ldr r0, =(RSTC_KEY | RSTC_URSTEN)
301 * Set exception stack pointers
303 ldr r0, =__stack_fiq_end
304 msr CPSR_c, #ARM_MODE_FIQ | 0xC0
306 ldr r0, =__stack_irq_end
307 msr CPSR_c, #ARM_MODE_IRQ | 0xC0
309 ldr r0, =__stack_abt_end
310 msr CPSR_c, #ARM_MODE_ABORT | 0xC0
312 ldr r0, =__stack_und_end
313 msr CPSR_c, #ARM_MODE_UNDEF | 0xC0
315 ldr r0, =__stack_svc_end
316 msr CPSR_c, #ARM_MODE_SVC | 0xC0
332 * Relocate .data section (Copy from ROM to RAM).
335 ldr r2, =__data_start
345 * Initialize user stack pointer.
347 ldr r13, =__stack_end