4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
35 * \author Francesco Sacchi <batt@develer.com>
37 * \brief AT91SAM7S256 CRT, adapted from NUt/OS, see license below.
41 * Copyright (C) 2005-2007 by egnite Software GmbH. All rights reserved.
43 * Redistribution and use in source and binary forms, with or without
44 * modification, are permitted provided that the following conditions
47 * 1. Redistributions of source code must retain the above copyright
48 * notice, this list of conditions and the following disclaimer.
49 * 2. Redistributions in binary form must reproduce the above copyright
50 * notice, this list of conditions and the following disclaimer in the
51 * documentation and/or other materials provided with the distribution.
52 * 3. Neither the name of the copyright holders nor the names of
53 * contributors may be used to endorse or promote products derived
54 * from this software without specific prior written permission.
56 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
58 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
59 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
60 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
61 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
62 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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66 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
69 * For additional information see http://www.ethernut.de/
73 #include "hw/hw_cpu.h"
74 #include <cpu/detect.h>
75 #include <cfg/cfg_arch.h>
78 #if CLOCK_FREQ != 48023000L
79 /* Avoid errors on nightly test */
80 #if !defined(ARCH_NIGHTTEST) || !(ARCH & ARCH_NIGHTTEST)
81 #error Clock registers set for 48MHz operation, revise following code if you want a different clock.
86 #if CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
88 * With a 18.420MHz cristal, master clock is:
89 * (((18.420 * PLL_MUL_VAL + 1) / PLL_DIV_VAL) / AT91MCK_PRES) = 48.023MHz
91 #define PLL_MUL_VAL 72 /**< Real multiplier value is PLL_MUL_VAL + 1! */
92 #define PLL_DIV_VAL 14
93 #define AT91MCK_PRES PMC_PRES_CLK_2
96 * Register I/O adresses.
99 #define MC_BASE 0xFFFFFF00
100 #define MC_FMR_OFF 0x00000060
101 #define MC_FWS_2R3W 0x00000100
103 #define AIC_BASE 0xFFFFF000
104 #define AIC_EOICR_OFF 0x00000130
105 #define AIC_IDCR_OFF 0x00000124
107 #define WDT_BASE 0xFFFFFD40
108 #define WDT_MR_OFF 0x00000004
109 #define WDT_WDDIS (1 << 15)
111 #define PMC_BASE 0xFFFFFC00
112 #define PMC_SR_OFF 0x00000068
113 #define PMC_MCKR_OFF 0x00000030
114 #define PMC_MOSCS (1 << 0)
115 #define PMC_LOCK (1 << 2)
116 #define PMC_MCKRDY (1 << 3)
117 #define PMC_CSS_MASK 0x00000003
118 #define PMC_CSS_PLL_CLK 0x00000003
119 #define PMC_PRES_MASK 0x0000001C
120 #define PMC_PRES_CLK_2 0x00000004
122 #define CKGR_MOR_OFF 0x00000020
123 #define CKGR_PLLR_OFF 0x0000002C
124 #define CKGR_MOSCEN (1 << 0)
125 #define CKGR_MUL_SHIFT 16
126 #define CKGR_PLLCOUNT_SHIFT 8
128 #define RSTC_MR 0xFFFFFD08
129 #define RSTC_KEY 0xA5000000
130 #define RSTC_URSTEN (1 << 0)
132 #define ARM_MODE_FIQ 0x11
133 #define ARM_MODE_IRQ 0x12
134 #define ARM_MODE_SVC 0x13
135 #define ARM_MODE_ABORT 0x17
136 #define ARM_MODE_UNDEF 0x1B
139 #error No register I/O definition for selected ARM CPU
144 * Section 0: Vector table and reset entry.
146 .section .vectors,"ax",%progbits
150 ldr pc, [pc, #24] /* Reset */
151 ldr pc, [pc, #24] /* Undefined instruction */
152 ldr pc, [pc, #24] /* Software interrupt */
153 ldr pc, [pc, #24] /* Prefetch abort */
154 ldr pc, [pc, #24] /* Data abort */
155 ldr pc, [pc, #24] /* Reserved */
158 * On IRQ the PC will be loaded from AIC_IVR, which
159 * provides the address previously set in AIC_SVR.
160 * The interrupt routine will be called in ARM_MODE_IRQ
161 * with IRQ disabled and FIQ unchanged.
163 ldr pc, [pc, #-0xF20] /* Interrupt request, auto vectoring. */
164 ldr pc, [pc, #-0xF20] /* Fast interrupt request, auto vectoring. */
169 .word __prefetch_abort
173 .set __undef, __xcpt_dummy_undef
175 .set __swi, __xcpt_dummy_swi
176 .weak __prefetch_abort
177 .set __prefetch_abort, __xcpt_dummy_pref
179 .set __data_abort, __xcpt_dummy_dab
181 /** .global __xcpt_dummy*/
197 * Hardware initialization.
199 .section .init, "ax", %progbits
203 * Use 2 cycles for flash access.
207 str r0, [r1, #MC_FMR_OFF]
210 * Disable all interrupts. Useful for debugging w/o target reset.
214 str r0, [r1, #AIC_EOICR_OFF]
215 str r0, [r1, #AIC_IDCR_OFF]
218 * The watchdog is enabled after processor reset. Disable it.
222 str r0, [r1, #WDT_MR_OFF]
225 * Enable the main oscillator. Set startup time of 6 * 8 slow
226 * clock cycles and wait until oscillator is stabilized.
230 orr r0, r0, #CKGR_MOSCEN
231 str r0, [r1, #CKGR_MOR_OFF]
233 ldr r0, [r1, #PMC_SR_OFF]
238 * Switch to Slow oscillator clock.
240 ldr r0, [r1, #PMC_MCKR_OFF]
241 and r0, r0, #~PMC_CSS_MASK
242 str r0, [r1, #PMC_MCKR_OFF]
244 ldr r0, [r1, #PMC_SR_OFF]
249 * Switch to prescaler div 1 factor.
251 ldr r0, [r1, #PMC_MCKR_OFF]
252 and r0, r0, #~PMC_PRES_MASK
253 str r0, [r1, #PMC_MCKR_OFF]
255 ldr r0, [r1, #PMC_SR_OFF]
261 * PLLfreq = crystal / divider * (multiplier + 1)
262 * Wait 28 clock cycles until PLL is locked.
264 ldr r0, =((PLL_MUL_VAL << CKGR_MUL_SHIFT) | (28 << CKGR_PLLCOUNT_SHIFT) | PLL_DIV_VAL)
266 str r0, [r1, #CKGR_PLLR_OFF]
268 ldr r0, [r1, #PMC_SR_OFF]
273 * Set master clock prescaler.
275 mov r0, #AT91MCK_PRES
276 str r0, [r1, #PMC_MCKR_OFF]
278 ldr r0, [r1, #PMC_SR_OFF]
283 * Switch to PLL clock. Trying to set this together with the
284 * prescaler fails (see datasheets).
286 ldr r0, [r1, #PMC_MCKR_OFF]
287 orr r0, r0, #PMC_CSS_PLL_CLK
288 str r0, [r1, #PMC_MCKR_OFF]
290 ldr r0, [r1, #PMC_SR_OFF]
295 * Enable external reset key.
297 ldr r0, =(RSTC_KEY | RSTC_URSTEN)
302 * Set exception stack pointers
304 ldr r0, =__stack_fiq_end
305 msr CPSR_c, #ARM_MODE_FIQ | 0xC0
307 ldr r0, =__stack_irq_end
308 msr CPSR_c, #ARM_MODE_IRQ | 0xC0
310 ldr r0, =__stack_abt_end
311 msr CPSR_c, #ARM_MODE_ABORT | 0xC0
313 ldr r0, =__stack_und_end
314 msr CPSR_c, #ARM_MODE_UNDEF | 0xC0
316 ldr r0, =__stack_svc_end
317 msr CPSR_c, #ARM_MODE_SVC | 0xC0
333 * Relocate .data section (Copy from ROM to RAM).
336 ldr r2, =__data_start
346 * Initialize user stack pointer.
348 ldr r13, =__stack_end