4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2006, 2008 Develer S.r.l. (http://www.develer.com/)
30 * All Rights Reserved.
33 * \brief Hardware-specific definitions
37 * \author Manuele Fanelli <qwert@develer.com>
42 //*****************************************************************************
44 // startup.c - Boot code for Stellaris.
46 // Copyright (c) 2005-2007 Luminary Micro, Inc. All rights reserved.
48 // Software License Agreement
50 // Luminary Micro, Inc. (LMI) is supplying this software for use solely and
51 // exclusively on LMI's microcontroller products.
53 // The software is owned by LMI and/or its suppliers, and is protected under
54 // applicable copyright laws. All rights are reserved. Any use in violation
55 // of the foregoing restrictions may subject the user to criminal sanctions
56 // under applicable laws, as well as to civil liability for the breach of the
57 // terms and conditions of this license.
59 // THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
60 // OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
61 // MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
62 // LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
63 // CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
65 // This is part of revision 1392 of the Stellaris Peripheral Driver Library.
67 //*****************************************************************************
69 //*****************************************************************************
71 // Forward declaration of the default fault handlers.
73 //*****************************************************************************
75 static void NmiSR(void);
76 static void FaultISR(void);
77 static void IntDefaultHandler(void);
79 //*****************************************************************************
81 // The entry point for the application.
83 //*****************************************************************************
84 extern int main(void);
86 //*****************************************************************************
88 // Reserve space for the system stack.
90 //*****************************************************************************
94 static unsigned long pulStack[STACK_SIZE];
96 //*****************************************************************************
98 // The minimal vector table for a Cortex M3. Note that the proper constructs
99 // must be placed on this to ensure that it ends up at physical address
102 //*****************************************************************************
103 __attribute__ ((section(".isr_vector")))
104 void (* const g_pfnVectors[])(void) =
106 (void (*)(void))((unsigned long)pulStack + sizeof(pulStack)),
107 // The initial stack pointer
108 ResetISR, // The reset handler
109 NmiSR, // The NMI handler
110 FaultISR, // The hard fault handler
111 IntDefaultHandler, // The MPU fault handler
112 IntDefaultHandler, // The bus fault handler
113 IntDefaultHandler, // The usage fault handler
118 IntDefaultHandler, // SVCall handler
119 IntDefaultHandler, // Debug monitor handler
121 IntDefaultHandler, // The PendSV handler
122 IntDefaultHandler, // The SysTick handler
123 IntDefaultHandler, // GPIO Port A
124 IntDefaultHandler, // GPIO Port B
125 IntDefaultHandler, // GPIO Port C
126 IntDefaultHandler, // GPIO Port D
127 IntDefaultHandler, // GPIO Port E
128 IntDefaultHandler, // UART0 Rx and Tx
129 IntDefaultHandler, // UART1 Rx and Tx
130 IntDefaultHandler, // SSI Rx and Tx
131 IntDefaultHandler, // I2C Master and Slave
132 IntDefaultHandler, // PWM Fault
133 IntDefaultHandler, // PWM Generator 0
134 IntDefaultHandler, // PWM Generator 1
135 IntDefaultHandler, // PWM Generator 2
136 IntDefaultHandler, // Quadrature Encoder
137 IntDefaultHandler, // ADC Sequence 0
138 IntDefaultHandler, // ADC Sequence 1
139 IntDefaultHandler, // ADC Sequence 2
140 IntDefaultHandler, // ADC Sequence 3
141 IntDefaultHandler, // Watchdog timer
142 IntDefaultHandler, // Timer 0 subtimer A
143 IntDefaultHandler, // Timer 0 subtimer B
144 IntDefaultHandler, // Timer 1 subtimer A
145 IntDefaultHandler, // Timer 1 subtimer B
146 IntDefaultHandler, // Timer 2 subtimer A
147 IntDefaultHandler, // Timer 2 subtimer B
148 IntDefaultHandler, // Analog Comparator 0
149 IntDefaultHandler, // Analog Comparator 1
150 IntDefaultHandler, // Analog Comparator 2
151 IntDefaultHandler, // System Control (PLL, OSC, BO)
152 IntDefaultHandler, // FLASH Control
153 IntDefaultHandler, // GPIO Port F
154 IntDefaultHandler, // GPIO Port G
155 IntDefaultHandler, // GPIO Port H
156 IntDefaultHandler, // UART2 Rx and Tx
157 IntDefaultHandler, // SSI1 Rx and Tx
158 IntDefaultHandler, // Timer 3 subtimer A
159 IntDefaultHandler, // Timer 3 subtimer B
160 IntDefaultHandler, // I2C1 Master and Slave
161 IntDefaultHandler, // Quadrature Encoder 1
162 IntDefaultHandler, // CAN0
163 IntDefaultHandler, // CAN1
165 IntDefaultHandler, // Ethernet
166 IntDefaultHandler // Hibernate
169 //*****************************************************************************
171 // The following are constructs created by the linker, indicating where the
172 // the "data" and "bss" segments reside in memory. The initializers for the
173 // for the "data" segment resides immediately following the "text" segment.
175 //*****************************************************************************
176 extern unsigned long _etext;
177 extern unsigned long _data;
178 extern unsigned long _edata;
179 extern unsigned long _bss;
180 extern unsigned long _ebss;
182 //*****************************************************************************
184 // This is the code that gets called when the processor first starts execution
185 // following a reset event. Only the absolutely necessary set is performed,
186 // after which the application supplied main() routine is called. Any fancy
187 // actions (such as making decisions based on the reset cause register, and
188 // resetting the bits in that register) are left solely in the hands of the
191 //*****************************************************************************
195 unsigned long *pulSrc, *pulDest;
198 // Copy the data segment initializers from flash to SRAM.
201 for(pulDest = &_data; pulDest < &_edata; )
203 *pulDest++ = *pulSrc++;
207 // Zero fill the bss segment.
209 for(pulDest = &_bss; pulDest < &_ebss; )
215 // Call the application's entry point.
220 //*****************************************************************************
222 // This is the code that gets called when the processor receives a NMI. This
223 // simply enters an infinite loop, preserving the system state for examination
226 //*****************************************************************************
231 // Enter an infinite loop.
238 //*****************************************************************************
240 // This is the code that gets called when the processor receives a fault
241 // interrupt. This simply enters an infinite loop, preserving the system state
242 // for examination by a debugger.
244 //*****************************************************************************
250 // Go into an infinite loop.
257 //*****************************************************************************
259 // This is the code that gets called when the processor receives an unexpected
260 // interrupt. This simply enters an infinite loop, preserving the system state
261 // for examination by a debugger.
263 //*****************************************************************************
265 IntDefaultHandler(void)
269 // Go into an infinite loop.