4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
35 * \author Daniele Basile <asterix@develer.com>
37 * AT91SAM7 Analog to Digital Converter.
47 * ADC control register
49 #define ADC_CR_OFF 0x00000000 ///< Control register offeset.
50 #define ADC_CR (*((reg32_t *)(ADC_BASE + ADC_CR_OFF))) ///< Control register address.
51 #define ADC_SWRST 0 ///< Software reset.
52 #define ADC_START 1 ///< Start conversion.
58 #define ADC_MR_OFF 0x00000004 ///< Mode register offeset.
59 #define ADC_MR (*((reg32_t *)(ADC_BASE + ADC_MR_OFF))) ///< Mode register address.
60 #define ADC_TRGEN 0 ///< Trigger enable.
62 #define ADC_TRGSEL_TIOA0 0x00000000 ///< TIOA output of the timer counter channel 0.
63 #define ADC_TRGSEL_TIOA1 0x00000002 ///< TIOA output of the timer counter channel 1.
64 #define ADC_TRGSEL_TIOA2 0x00000004 ///< TIOA output of the timer counter channel 2.
65 #define ADC_TRGSEL_EXT 0x0000000C ///< External trigger.
67 #define ADC_LOWRES 4 ///< Resolution 0: 10-bit, 1: 8-bit.
68 #define ADC_SLEEP 5 ///< Sleep mode.
71 * Prescaler rate selection.
72 * ADCClock = MCK / ((ADC_PRESCALER_VALUE + 1) * 2)
74 #define ADC_PRESCALER_MASK 0x00003F00 ///< Prescaler rate selection mask.
75 #define ADC_PRESCALER_SHIFT 8 ///< Prescale rate selection shift.
79 * Startup time = (ADC_STARTUP_VALUE + 1) * 8 /ADCClock
81 #define ADC_STARTUP_MASK 0x001F0000 ///< Start up timer mask.
82 #define ADC_STARTUP_SHIFT 16 ///< Start up timer shift.
87 * Sample & hold time = (ADC_SHTIM_VALUE + 1) * 8 /ADCClock
89 #define ADC_SHTIME_MASK 0x0F000000 ///< Sample & hold time mask.
90 #define ADC_SHTIME_SHIFT 24 ///< Sample & hold time shift.
94 * ADC channel enable register
96 #define ADC_CHER_OFF 0x00000010 ///< Channel enable register offeset.
97 #define ADC_CHER (*((reg32_t *)(ADC_BASE + ADC_CHER_OFF))) ///< Channel enable register address.
100 * ADC channel disable register
102 #define ADC_CHDR_OFF 0x00000014 ///< Channel disable register offeset.
103 #define ADC_CHDR (*((reg32_t *)(ADC_BASE + ADC_CHDR_OFF))) ///< Channel disable register address.
106 * ADC channel status register
108 #define ADC_CHSR_OFF 0x00000018 ///< Channel status register offeset.
109 #define ADC_CHSR (*((reg32_t *)(ADC_BASE + ADC_CHSR_OFF))) ///< Channel status register address.
111 #define ADC_CH_MASK 0x000000FF ///< Channel mask.
112 #define ADC_CH0 0 ///< Channel 0
113 #define ADC_CH1 1 ///< Channel 1
114 #define ADC_CH2 2 ///< Channel 2
115 #define ADC_CH3 3 ///< Channel 3
116 #define ADC_CH4 4 ///< Channel 4
117 #define ADC_CH5 5 ///< Channel 5
118 #define ADC_CH6 6 ///< Channel 6
119 #define ADC_CH7 7 ///< Channel 7
122 * ADC status register
124 #define ADC_SR_OFF 0x0000001C ///< Status register offeset.
125 #define ADC_SR (*((reg32_t *)(ADC_BASE + ADC_SR_OFF))) ///< Status register address.
128 * ADC Interrupt enable register.
130 #define ADC_IER_OFF 0x00000024 ///< Interrupt enable register offeset.
131 #define ADC_IER (*((reg32_t *)(ADC_BASE + ADC_IER_OFF))) ///< Interrupt enable register.
134 * ADC Interrupt disable register.
136 #define ADC_IDR_OFF 0x00000028 ///< Interrupt disable register offeset.
137 #define ADC_IDR (*((reg32_t *)(ADC_BASE + ADC_IDR_OFF))) ///< Interrupt disable register.
140 * ADC Interrupt mask register.
142 #define ADC_IMR_OFF 0x0000002C ///< Interrupt mask register offeset.
143 #define ADC_IMR (*((reg32_t *)(ADC_BASE + ADC_IMR_OFF))) ///< Interrupt mask register.
145 #define ADC_EOC_MASK 0x000000FF ///< End of converison mask.
146 #define ADC_EOC0 0 ///< End of conversion channel 0.
147 #define ADC_EOC1 1 ///< End of conversion channel 1.
148 #define ADC_EOC2 2 ///< End of conversion channel 2.
149 #define ADC_EOC3 3 ///< End of conversion channel 3.
150 #define ADC_EOC4 4 ///< End of conversion channel 4.
151 #define ADC_EOC5 5 ///< End of conversion channel 5.
152 #define ADC_EOC6 6 ///< End of conversion channel 6.
153 #define ADC_EOC7 7 ///< End of conversion channel 7.
155 #define ADC_OVRE0 8 ///< Overrun error channel 0.
156 #define ADC_OVRE1 9 ///< Overrun error channel 1.
157 #define ADC_OVRE2 10 ///< Overrun error channel 2.
158 #define ADC_OVRE3 11 ///< Overrun error channel 3.
159 #define ADC_OVRE4 12 ///< Overrun error channel 4.
160 #define ADC_OVRE5 13 ///< Overrun error channel 5.
161 #define ADC_OVRE6 14 ///< Overrun error channel 6.
162 #define ADC_OVRE7 15 ///< Overrun error channel 7.
164 #define ADC_DRDY 16 ///< Data ready.
165 #define ADC_GOVRE 17 ///< General overrun error.
166 #define ADC_ENDRX 18 ///< End of RX buffer.
167 #define ADC_RXBUFF 19 ///< Rx buffer full.
170 * ADC last convert data register.
172 #define ADC_LCDR_OFF 0x00000020 ///< Last converted data register offeset.
173 #define ADC_LCDR (*((reg32_t *)(ADC_BASE + ADC_LCDR_OFF))) ///< Last converted data register.
176 * ADC channel data register.
180 #define ADC_CDR0_OFF 0x00000030 ///< Channel data register 0 offeset.
181 #define ADC_CDR1_OFF 0x00000034 ///< Channel data register 1 offeset.
182 #define ADC_CDR2_OFF 0x00000038 ///< Channel data register 2 offeset.
183 #define ADC_CDR3_OFF 0x0000003C ///< Channel data register 3 offeset.
184 #define ADC_CDR4_OFF 0x00000040 ///< Channel data register 4 offeset.
185 #define ADC_CDR5_OFF 0x00000044 ///< Channel data register 5 offeset.
186 #define ADC_CDR6_OFF 0x00000048 ///< Channel data register 6 offeset.
187 #define ADC_CDR7_OFF 0x0000004C ///< Channel data register 7 offeset.
189 #define ADC_CDR0 (*((reg32_t *)(ADC_BASE + ADC_CDR0_OFF))) ///< Channel data register 0.
190 #define ADC_CDR1 (*((reg32_t *)(ADC_BASE + ADC_CDR1_OFF))) ///< Channel data register 1.
191 #define ADC_CDR2 (*((reg32_t *)(ADC_BASE + ADC_CDR2_OFF))) ///< Channel data register 2.
192 #define ADC_CDR3 (*((reg32_t *)(ADC_BASE + ADC_CDR3_OFF))) ///< Channel data register 3.
193 #define ADC_CDR4 (*((reg32_t *)(ADC_BASE + ADC_CDR4_OFF))) ///< Channel data register 4.
194 #define ADC_CDR5 (*((reg32_t *)(ADC_BASE + ADC_CDR5_OFF))) ///< Channel data register 5.
195 #define ADC_CDR6 (*((reg32_t *)(ADC_BASE + ADC_CDR6_OFF))) ///< Channel data register 6.
196 #define ADC_CDR7 (*((reg32_t *)(ADC_BASE + ADC_CDR7_OFF))) ///< Channel data register 7.
199 #endif /* AT91_ADC_H */