4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
35 * \author Francesco Sacchi <batt@develer.com>
37 * AT91 advanced interrupt controller.
38 * This file is based on NUT/OS implementation. See license below.
42 * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
44 * Redistribution and use in source and binary forms, with or without
45 * modification, are permitted provided that the following conditions
48 * 1. Redistributions of source code must retain the above copyright
49 * notice, this list of conditions and the following disclaimer.
50 * 2. Redistributions in binary form must reproduce the above copyright
51 * notice, this list of conditions and the following disclaimer in the
52 * documentation and/or other materials provided with the distribution.
53 * 3. Neither the name of the copyright holders nor the names of
54 * contributors may be used to endorse or promote products derived
55 * from this software without specific prior written permission.
57 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
58 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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60 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
61 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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63 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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67 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
70 * For additional information see http://www.ethernut.de/
76 #include <cfg/compiler.h>
81 * Source mode register array.
83 #define AIC_SMR(i) (*((reg32_t *)(AIC_BASE + (i) * 4)))
87 * Priority levels can be between 0 (lowest) and 7 (highest).
89 #define AIC_PRIOR_MASK 0x00000007
92 * Interrupt source type mask.
93 * Internal interrupts can level sensitive or edge triggered.
95 * External interrupts can triggered on positive or negative levels or
96 * on rising or falling edges.
99 #define AIC_SRCTYPE_MASK 0x00000060
101 #define AIC_SRCTYPE_INT_LEVEL_SENSITIVE 0x00000000 ///< Internal level sensitive.
102 #define AIC_SRCTYPE_INT_EDGE_TRIGGERED 0x00000020 ///< Internal edge triggered.
103 #define AIC_SRCTYPE_EXT_LOW_LEVEL 0x00000000 ///< External low level.
104 #define AIC_SRCTYPE_EXT_NEGATIVE_EDGE 0x00000020 ///< External falling edge.
105 #define AIC_SRCTYPE_EXT_HIGH_LEVEL 0x00000040 ///< External high level.
106 #define AIC_SRCTYPE_EXT_POSITIVE_EDGE 0x00000060 ///< External rising edge.
111 * Type for interrupt handlers.
113 typedef void (*irq_handler_t)(void);
115 /** Interrupt Source Vector Registers */
117 /** Source vector register array.
119 * Stores the addresses of the corresponding interrupt handlers.
121 #define AIC_SVR(i) (*((volatile irq_handler_t *)(AIC_BASE + 0x80 + (i) * 4)))
124 /** Interrupt Vector Register */
126 #define AIC_IVR_OFF 0x00000100 ///< IRQ vector register offset.
127 #define AIC_IVR (*((reg32_t *)(AIC_BASE + AIC_IVR_OFF))) ///< IRQ vector register address.
130 /** Fast Interrupt Vector Register */
132 #define AIC_FVR_OFF 0x00000104 ///< FIQ vector register offset.
133 #define AIC_FVR (*((reg32_t *)(AIC_BASE + AIC_FVR_OFF))) ///< FIQ vector register address.
136 /** Interrupt Status Register */
138 #define AIC_ISR_OFF 0x00000108 ///< Interrupt status register offset.
139 #define AIC_ISR (*((reg32_t *)(AIC_BASE + AIC_ISR_OFF))) ///< Interrupt status register address.
140 #define AIC_IRQID_MASK 0x0000001F ///< Current interrupt identifier mask.
143 /** Interrupt Pending Register */
145 #define AIC_IPR_OFF 0x0000010C ///< Interrupt pending register offset.
146 #define AIC_IPR (*((reg32_t *)(AIC_BASE + AIC_IPR_OFF))) ///< Interrupt pending register address.
149 /** Interrupt Mask Register */
151 #define AIC_IMR_OFF 0x00000110 ///< Interrupt mask register offset.
152 #define AIC_IMR (*((reg32_t *)(AIC_BASE + AIC_IMR_OFF))) ///< Interrupt mask register address.
155 /** Interrupt Core Status Register */
157 #define AIC_CISR_OFF 0x00000114 ///< Core interrupt status register offset.
158 #define AIC_CISR (*((reg32_t *)(AIC_BASE + AIC_CISR_OFF))) ///< Core interrupt status register address.
159 #define AIC_NFIQ 1 ///< Core FIQ Status
160 #define AIC_NIRQ 2 ///< Core IRQ Status
163 /** Interrupt Enable Command Register */
165 #define AIC_IECR_OFF 0x00000120 ///< Interrupt enable command register offset.
166 #define AIC_IECR (*((reg32_t *)(AIC_BASE + AIC_IECR_OFF))) ///< Interrupt enable command register address.
169 /** Interrupt Disable Command Register */
171 #define AIC_IDCR_OFF 0x00000124 ///< Interrupt disable command register offset.
172 #define AIC_IDCR (*((reg32_t *)(AIC_BASE + AIC_IDCR_OFF))) ///< Interrupt disable command register address.
175 /** Interrupt Clear Command Register */
177 #define AIC_ICCR_OFF 0x00000128 ///< Interrupt clear command register offset.
178 #define AIC_ICCR (*((reg32_t *)(AIC_BASE + AIC_ICCR_OFF))) ///< Interrupt clear command register address.
181 /** Interrupt Set Command Register */
183 #define AIC_ISCR_OFF 0x0000012C ///< Interrupt set command register offset.
184 #define AIC_ISCR (*((reg32_t *)(AIC_BASE + AIC_ISCR_OFF))) ///< Interrupt set command register address.
187 /** End Of Interrupt Command Register */
189 #define AIC_EOICR_OFF 0x00000130 ///< End of interrupt command register offset.
190 #define AIC_EOICR (*((reg32_t *)(AIC_BASE + AIC_EOICR_OFF))) ///< End of interrupt command register address.
193 /** Spurious Interrupt Vector Register */
195 #define AIC_SPU_OFF 0x00000134 ///< Spurious vector register offset.
196 #define AIC_SPU (*((reg32_t *)(AIC_BASE + AIC_SPU_OFF)== ///< Spurious vector register address.
199 /** Debug Control Register */
201 #define AIC_DCR_OFF 0x0000138 ///< Debug control register offset.
202 #define AIC_DCR (*((reg32_t *)(AIC_BASE + AIC_DCR_OFF))) ///< Debug control register address.
205 /** Fast Forcing Enable Register */
207 #define AIC_FFER_OFF 0x00000140 ///< Fast forcing enable register offset.
208 #define AIC_FFER (*((reg32_t *)(AIC_BASE + AIC_FFER_OFF))) ///< Fast forcing enable register address.
211 /** Fast Forcing Disable Register */
213 #define AIC_FFDR_OFF 0x00000144 ///< Fast forcing disable register address.
214 #define AIC_FFDR (*((reg32_t *)(AIC_BASE + AIC_FFDR_OFF))) ///< Fast forcing disable register address.
217 /** Fast Forcing Status Register */
219 #define AIC_FFSR_OFF 0x00000148 ///< Fast forcing status register address.
220 #define AIC_FFSR (*((reg32_t *)(AIC_BASE + AIC_FFSR_OFF))) ///< Fast forcing status register address.
223 #endif /* AT91_AIC_H */