4 * This file is part of BeRTOS.
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14 * GNU General Public License for more details.
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20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
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29 * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
35 * \author Francesco Sacchi <batt@develer.com>
38 * This file is based on NUT/OS implementation. See license below.
42 * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
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45 * modification, are permitted provided that the following conditions
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70 * For additional information see http://www.ethernut.de/
75 #define DBGU_CR (*((reg32_t *)(DBGU_BASE + US_CR_OFF))) ///<DBGU control register address.
76 #define DBGU_MR (*((reg32_t *)(DBGU_BASE + US_MR_OFF))) ///<DBGU mode register address.
77 #define DBGU_IER (*((reg32_t *)(DBGU_BASE + US_IER_OFF))) ///<DBGU interrupt enable register address.
78 #define DBGU_IDR (*((reg32_t *)(DBGU_BASE + US_IDR_OFF))) ///<DBGU interrupt disable register address.
79 #define DBGU_IMR (*((reg32_t *)(DBGU_BASE + US_IMR_OFF))) ///<DBGU interrupt mask register address.
80 #define DBGU_SR (*((reg32_t *)(DBGU_BASE + US_CSR_OFF))) ///<DBGU status register address.
81 #define DBGU_RHR (*((reg32_t *)(DBGU_BASE + US_RHR_OFF))) ///<DBGU receiver holding register address.
82 #define DBGU_THR (*((reg32_t *)(DBGU_BASE + US_THR_OFF))) ///<DBGU transmitter holding register address.
83 #define DBGU_BRGR (*((reg32_t *)(DBGU_BASE + US_BRGR_OFF))) ///<DBGU baud rate register address.
85 #define DBGU_CIDR_OFF 0x00000040 ///<DBGU chip ID register offset.
86 #define DBGU_CIDR (*((reg32_t *)(DBGU_BASE + DBGU_CIDR_OFF))) ///<DBGU chip ID register.
88 #define DBGU_EXID_OFF 0x00000044 ///<DBGU chip ID extension register offset.
89 #define DBGU_EXID (*((reg32_t *)(DBGU_BASE + DBGU_EXID_OFF))) ///<DBGU chip ID extension register.
91 #define DBGU_FNR_OFF 0x00000048 ///<DBGU force NTRST register offset.
92 #define DBGU_FNR (*((reg32_t *)(DBGU_BASE + DBGU_FNR_OFF))) ///<DBGU force NTRST register.
94 #if defined(DBGU_HAS_PDC)
95 #define DBGU_RPR (*((reg32_t *)(DBGU_BASE + PERIPH_RPR_OFF))) ///<PDC receive pointer register.
96 #define DBGU_RCR (*((reg32_t *)(DBGU_BASE + PERIPH_RCR_OFF))) ///<PDC receive counter register.
97 #define DBGU_TPR (*((reg32_t *)(DBGU_BASE + PERIPH_TPR_OFF))) ///<PDC transmit pointer register.
98 #define DBGU_TCR (*((reg32_t *)(DBGU_BASE + PERIPH_TCR_OFF))) ///<PDC transmit counter register.
99 #define DBGU_RNPR (*((reg32_t *)(DBGU_BASE + PERIPH_RNPR_OFF))) ///<PDC receive next pointer register.
100 #define DBGU_RNCR (*((reg32_t *)(DBGU_BASE + PERIPH_RNCR_OFF))) ///<PDC receive next counter register.
101 #define DBGU_TNPR (*((reg32_t *)(DBGU_BASE + PERIPH_TNPR_OFF))) ///<PDC transmit next pointer register.
102 #define DBGU_TNCR (*((reg32_t *)(DBGU_BASE + PERIPH_TNCR_OFF))) ///<PDC transmit next counter register.
103 #define DBGU_PTCR (*((reg32_t *)(DBGU_BASE + PERIPH_PTCR_OFF))) ///<PDC transfer control register.
104 #define DBGU_PTSR (*((reg32_t *)(DBGU_BASE + PERIPH_PTSR_OFF))) ///<PDC transfer status register.
107 #endif /* AT91_DBGU_H */