4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2009 Develer S.r.l. (http://www.develer.com/)
33 * \author Daniele Basile <asterix@develer.com>
35 * AT91 Ethernet MAC 10/100 controller.
36 * This file is based on NUT/OS implementation. See license below.
40 * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
42 * Redistribution and use in source and binary forms, with or without
43 * modification, are permitted provided that the following conditions
46 * 1. Redistributions of source code must retain the above copyright
47 * notice, this list of conditions and the following disclaimer.
48 * 2. Redistributions in binary form must reproduce the above copyright
49 * notice, this list of conditions and the following disclaimer in the
50 * documentation and/or other materials provided with the distribution.
51 * 3. Neither the name of the copyright holders nor the names of
52 * contributors may be used to endorse or promote products derived
53 * from this software without specific prior written permission.
55 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
56 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
57 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
58 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
59 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
60 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
61 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
62 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
63 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
65 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
68 * For additional information see http://www.ethernut.de/
77 * Network Control Register
81 #define EMAC_NCR_OFF 0x00000000 ///< Network control register offset.
82 #define EMAC_NCR (*((reg32_t *)(EMAC_BASE + EMAC_NCR_OFF))) ///< Network Control register address.
83 #define EMAC_LB 0 ///< PHY loopback.
84 #define EMAC_LLB 1 ///< EMAC loopback.
85 #define EMAC_RE 2 ///< Receive enable.
86 #define EMAC_TE 3 ///< Transmit enable.
87 #define EMAC_MPE 4 ///< Management port enable.
88 #define EMAC_CLRSTAT 5 ///< Clear statistics registers.
89 #define EMAC_INCSTAT 6 ///< Increment statistics registers.
90 #define EMAC_WESTAT 7 ///< Write enable for statistics registers.
91 #define EMAC_BP 8 ///< Back pressure.
92 #define EMAC_TSTART 9 ///< Start Transmission.
93 #define EMAC_THALT 10 ///< Transmission halt.
95 //#define EMAC_TPFR 11 ///< Transmit pause frame.
96 //#define EMAC_TZQ 12 ///< Transmit zero quantum pause frame.
100 * Network Configuration Register
104 #define EMAC_NCFGR_OFF 0x00000004 ///< Network configuration register offset.
105 #define EMAC_NCFGR (*((reg32_t *)(EMAC_BASE + EMAC_NCFGR_OFF))) ///< Network configuration register address.
106 #define EMAC_SPD 0 ///< Speed, set for 100Mb.
107 #define EMAC_FD 1 ///< Full duplex.
108 #define EMAC_JFRAME 3 ///< Jumbo Frames.
109 #define EMAC_CAF 4 ///< Copy all frames.
110 #define EMAC_NBC 5 ///< No broadcast.
111 #define EMAC_MTI 6 ///< Multicast hash event enable.
112 #define EMAC_UNI 7 ///< Unicast hash enable.
113 #define EMAC_BIG 8 ///< Receive 1522 bytes.
115 //#define EMAC_EAE 9 ///< External address match enable.
116 #define EMAC_CLK 0x00000C00 ///< Clock divider mask.
117 #define EMAC_CLK_HCLK_8 0x00000000 ///< HCLK divided by 8.
118 #define EMAC_CLK_HCLK_16 0x00000400 ///< HCLK divided by 16.
119 #define EMAC_CLK_HCLK_32 0x00000800 ///< HCLK divided by 32.
120 #define EMAC_CLK_HCLK_64 0x00000C00 ///< HCLK divided by 64.
121 #define EMAC_RTY 12 ///< Retry test.
122 #define EMAC_PAE 13 ///< Pause enable.
123 #define EMAC_RBOF 0x0000C000 ///< Receive buffer offset.
124 #define EMAC_RBOF_OFFSET_0 0x00000000 ///< No offset from start of receive buffer.
125 #define EMAC_RBOF_OFFSET_1 0x00004000 ///< One byte offset from start of receive buffer.
126 #define EMAC_RBOF_OFFSET_2 0x00008000 ///< Two bytes offset from start of receive buffer.
127 #define EMAC_RBOF_OFFSET_3 0x0000C000 ///< Three bytes offset from start of receive buffer.
128 #define EMAC_RLCE 16 ///< Receive length field checking enable.
129 #define EMAC_DRFCS 17 ///< Discard receive FCS.
130 #define EMAC_EFRHD 18 ///< Allow receive during transmit in half duplex.
131 #define EMAC_IRXFCS 19 ///< Ignore received FCS.
135 * Network Status Register
139 #define EMAC_NSR_OFF 0x00000008 ///< Network Status register offset.
140 #define EMAC_NSR (*((reg32_t *)(EMAC_BASE + EMAC_NSR_OFF))) ///< Network Status register address.
142 //#define EMAC_LINKR 0 ///< .
143 #define EMAC_MDIO 1 ///< Status of MDIO input pin.
144 #define EMAC_IDLE 2 ///< Set when PHY is running.
148 * Transmit Status Register
151 #define EMAC_TSR_OFF 0x00000014 ///< Transmit Status register offset.
152 #define EMAC_TSR (*((reg32_t *)(EMAC_BASE + EMAC_TSR_OFF))) ///< Transmit Status register address.
154 #define EMAC_UBR 0 ///< Used bit read.
155 #define EMAC_COL 1 ///< Collision occurred.
156 #define EMAC_RLES 2 ///< Retry limit exceeded.
157 #define EMAC_TGO 3 ///< Transmit active.
158 #define EMAC_BEX 4 ///< Buffers exhausted mid frame.
159 #define EMAC_COMP 5 ///< Transmit complete.
160 #define EMAC_UND 6 ///< Transmit underrun.
164 * Buffer Queue Pointer Register
168 #define EMAC_RBQP_OFF 0x00000018 ///< Receive buffer queue pointer.
169 #define EMAC_RBQP (*((reg32_t *)(EMAC_BASE + EMAC_RBQP_OFF))) ///< Receive buffer queue pointer.
170 #define EMAC_TBQP_OFF 0x0000001C ///< Transmit buffer queue pointer.
171 #define EMAC_TBQP (*((reg32_t *)(EMAC_BASE + EMAC_TBQP_OFF))) ///< Transmit buffer queue pointer.
175 * Receive Status Register
178 #define EMAC_RSR_OFF 0x00000020 ///< Receive status register offset.
179 #define EMAC_RSR (*((reg32_t *)(EMAC_BASE + EMAC_RSR_OFF))) ///< Receive status register address.
180 #define EMAC_BNA 0 ///< Buffer not available.
181 #define EMAC_REC 1 ///< Frame received.
182 #define EMAC_OVR 2 ///< Receive overrun.
185 /** Interrupt Registers */
187 #define EMAC_ISR_OFF 0x00000024 ///< Status register offset.
188 #define EMAC_ISR (*((reg32_t *)(EMAC_BASE + EMAC_ISR_OFF))) ///< Status register address.
189 #define EMAC_IER_OFF 0x00000028 ///< Enable register offset.
190 #define EMAC_IER (*((reg32_t *)(EMAC_BASE + EMAC_IER_OFF))) ///< Enable register address.
191 #define EMAC_IDR_OFF 0x0000002C ///< Disable register offset.
192 #define EMAC_IDR (*((reg32_t *)(EMAC_BASE + EMAC_IDR_OFF))) ///< Disable register address.
193 #define EMAC_IMR_OFF 0x00000030 ///< Mask register offset.
194 #define EMAC_IMR (*((reg32_t *)(EMAC_BASE + EMAC_IMR_OFF))) ///< Mask register address.
196 #define EMAC_MFD 0 ///< Management frame done.
197 #define EMAC_RCOMP 1 ///< Receive complete.
198 #define EMAC_RXUBR 2 ///< Receive used bit read.
199 #define EMAC_TXUBR 3 ///< Transmit used bit read.
200 #define EMAC_TUND 4 ///< Ethernet transmit buffer underrun.
201 #define EMAC_RLEX 5 ///< Retry limit exceeded.
202 #define EMAC_TXERR 6 ///< Transmit error.
203 #define EMAC_TCOMP 7 ///< Transmit complete.
205 //#define EMAC_LINK 8 ///< .
206 #define EMAC_ROVR 10 ///< Receive overrun.
207 #define EMAC_HRESP 11 ///< DMA bus error.
208 #define EMAC_PFR 12 ///< Pause frame received.
209 #define EMAC_PTZ 13 ///< Pause time zero.
213 * PHY Maintenance Register
217 #define EMAC_MAN_OFF 0x00000034 ///< PHY maintenance register offset.
218 #define EMAC_MAN (*((reg32_t *)(EMAC_BASE + EMAC_MAN_OFF))) ///< PHY maintenance register address.
219 #define EMAC_DATA 0x0000FFFF ///< PHY data mask.
220 #define EMAC_CODE 0x00020000 ///< Fixed value.
221 #define EMAC_REGA 0x007C0000 ///< PHY register address mask.
222 #define EMAC_REGA_SHIFT 18 ///< PHY register address mask.
223 #define EMAC_PHYA 0x0F800000 ///< PHY address mask.
224 #define EMAC_PHYA_SHIFT 23 ///< PHY address mask.
225 #define EMAC_RW 0x30000000 ///< PHY read/write command mask.
226 #define EMAC_RW_READ 0x20000000 ///< PHY read command.
227 #define EMAC_RW_WRITE 0x10000000 ///< PHY write command.
228 #define EMAC_SOF 0x40000000 ///< Fixed value.
232 * Pause Time Register
236 #define EMAC_PTR_OFF 0x00000038 ///< Pause time register offset.
237 #define EMAC_PTR (*((reg32_t *)(EMAC_BASE + EMAC_PTR_OFF))) ///< Pause time register address.
238 #define EMAC_PTIME 0x0000FFFF ///< Pause time mask.
242 * Statistics Registers
245 #define EMAC_PFRR_OFF 0x0000003C ///< Pause frames received register offset.
246 #define EMAC_PFRR (*((reg32_t *)(EMAC_BASE + EMAC_PFRR_OFF))) ///< Pause frames received register address.
247 #define EMAC_FTO_OFF 0x00000040 ///< Frames transmitted OK register offset.
248 #define EMAC_FTO (*((reg32_t *)(EMAC_BASE + EMAC_FTO_OFF))) ///< Frames transmitted OK register address.
249 #define EMAC_SCF_OFF 0x00000044 ///< Single collision frame register offset.
250 #define EMAC_SCF (*((reg32_t *)(EMAC_BASE + EMAC_SCF_OFF))) ///< Single collision frame register address.
251 #define EMAC_MCF_OFF 0x00000048 ///< Multiple collision frame register offset.
252 #define EMAC_MCF (*((reg32_t *)(EMAC_BASE + EMAC_MCF_OFF))) ///< Multiple collision frame register address.
253 #define EMAC_FRO_OFF 0x0000004C ///< Frames received OK register offset.
254 #define EMAC_FRO (*((reg32_t *)(EMAC_BASE + EMAC_FRO_OFF))) ///< Frames received OK register address.
255 #define EMAC_FCSE_OFF 0x00000050 ///< Frame check sequence error register offset.
256 #define EMAC_FCSE (*((reg32_t *)(EMAC_BASE + EMAC_FCSE_OFF))) ///< Frame check sequence error register address.
257 #define EMAC_ALE_OFF 0x00000054 ///< Alignment error register offset.
258 #define EMAC_ALE (*((reg32_t *)(EMAC_BASE + EMAC_ALE_OFF))) ///< Alignment error register address.
259 #define EMAC_DTF_OFF 0x00000058 ///< Deferred transmission frame register offset.
260 #define EMAC_DTF (*((reg32_t *)(EMAC_BASE + EMAC_DTF_OFF))) ///< Deferred transmission frame register address.
261 #define EMAC_LCOL_OFF 0x0000005C ///< Late collision register offset.
262 #define EMAC_LCOL (*((reg32_t *)(EMAC_BASE + EMAC_LCOL_OFF))) ///< Late collision register address.
263 #define EMAC_ECOL_OFF 0x00000060 ///< Excessive collision register offset.
264 #define EMAC_ECOL (*((reg32_t *)(EMAC_BASE + EMAC_ECOL_OFF))) ///< Excessive collision register address.
265 #define EMAC_TUNDR_OFF 0x00000064 ///< Transmit underrun error register offset.
266 #define EMAC_TUNDR (*((reg32_t *)(EMAC_BASE + EMAC_TUNDR_OFF))) ///< Transmit underrun error register address.
267 #define EMAC_CSE_OFF 0x00000068 ///< Carrier sense error register offset.
268 #define EMAC_CSE (*((reg32_t *)(EMAC_BASE + EMAC_CSE_OFF))) ///< Carrier sense error register address.
269 #define EMAC_RRE_OFF 0x0000006C ///< Receive resource error register offset.
270 #define EMAC_RRE (*((reg32_t *)(EMAC_BASE + EMAC_RRE_OFF))) ///< Receive resource error register address.
271 #define EMAC_ROV_OFF 0x00000070 ///< Receive overrun errors register offset.
272 #define EMAC_ROV (*((reg32_t *)(EMAC_BASE + EMAC_ROV_OFF))) ///< Receive overrun errors register address.
273 #define EMAC_RSE_OFF 0x00000074 ///< Receive symbol errors register offset.
274 #define EMAC_RSE (*((reg32_t *)(EMAC_BASE + EMAC_RSE_OFF))) ///< Receive symbol errors register address.
275 #define EMAC_ELE_OFF 0x00000078 ///< Excessive length errors register offset.
276 #define EMAC_ELE (*((reg32_t *)(EMAC_BASE + EMAC_ELE_OFF))) ///< Excessive length errors register address.
277 #define EMAC_RJA_OFF 0x0000007C ///< Receive jabbers register offset.
278 #define EMAC_RJA (*((reg32_t *)(EMAC_BASE + EMAC_RJA_OFF))) ///< Receive jabbers register address.
279 #define EMAC_USF_OFF 0x00000080 ///< Undersize frames register offset.
280 #define EMAC_USF (*((reg32_t *)(EMAC_BASE + EMAC_USF_OFF))) ///< Undersize frames register address.
281 #define EMAC_STE_OFF 0x00000084 ///< SQE test error register offset.
282 #define EMAC_STE (*((reg32_t *)(EMAC_BASE + EMAC_STE_OFF))) ///< SQE test error register address.
283 #define EMAC_RLE_OFF 0x00000088 ///< Receive length field mismatch register offset.
284 #define EMAC_RLE (*((reg32_t *)(EMAC_BASE + EMAC_RLE_OFF))) ///< Receive length field mismatch register address.
286 //#define EMAC_TPF_OFF 0x0000008C ///< Transmitted pause frames register offset.
287 //#define EMAC_TPF (*((reg32_t *)(EMAC_BASE + EMAC_TPF_OFF) ///< Transmitted pause frames register address.
291 * MAC Adressing Registers
295 #define EMAC_HRB_OFF 0x00000090 ///< Hash address bottom[31:0].
296 #define EMAC_HRB (*((reg32_t *)(EMAC_BASE + EMAC_HRB_OFF))) ///< Hash address bottom[31:0].
297 #define EMAC_HRT_OFF 0x00000094 ///< Hash address top[63:32].
298 #define EMAC_HRT (*((reg32_t *)(EMAC_BASE + EMAC_HRT_OFF))) ///< Hash address top[63:32].
299 #define EMAC_SA1L_OFF 0x00000098 ///< Specific address 1 bottom, first 4 bytes.
300 #define EMAC_SA1L (*((reg32_t *)(EMAC_BASE + EMAC_SA1L_OFF))) ///< Specific address 1 bottom, first 4 bytes.
301 #define EMAC_SA1H_OFF 0x0000009C ///< Specific address 1 top, last 2 bytes.
302 #define EMAC_SA1H (*((reg32_t *)(EMAC_BASE + EMAC_SA1H_OFF))) ///< Specific address 1 top, last 2 bytes.
303 #define EMAC_SA2L_OFF 0x000000A0 ///< Specific address 2 bottom, first 4 bytes.
304 #define EMAC_SA2L (*((reg32_t *)(EMAC_BASE + EMAC_SA2L_OFF))) ///< Specific address 2 bottom, first 4 bytes.
305 #define EMAC_SA2H_OFF 0x000000A4 ///< Specific address 2 top, last 2 bytes.
306 #define EMAC_SA2H (*((reg32_t *)(EMAC_BASE + EMAC_SA2H_OFF))) ///< Specific address 2 top, last 2 bytes.
307 #define EMAC_SA3L_OFF 0x000000A8 ///< Specific address 3 bottom, first 4 bytes.
308 #define EMAC_SA3L (*((reg32_t *)(EMAC_BASE + EMAC_SA3L_OFF))) ///< Specific address 3 bottom, first 4 bytes.
309 #define EMAC_SA3H_OFF 0x000000AC ///< Specific address 3 top, last 2 bytes.
310 #define EMAC_SA3H (*((reg32_t *)(EMAC_BASE + EMAC_SA3H_OFF))) ///< Specific address 3 top, last 2 bytes.
311 #define EMAC_SA4L_OFF 0x000000B0 ///< Specific address 4 bottom, first 4 bytes.
312 #define EMAC_SA4L (*((reg32_t *)(EMAC_BASE + EMAC_SA4L_OFF))) ///< Specific address 4 bottom, first 4 bytes.
313 #define EMAC_SA4H_OFF 0x000000B4 ///< Specific address 4 top, last 2 bytes.
314 #define EMAC_SA4H (*((reg32_t *)(EMAC_BASE + EMAC_SA4H_OFF))) ///< Specific address 4 top, last 2 bytes.
322 #define EMAC_TID_OFF 0x000000B8 ///< Type ID checking register offset.
323 #define EMAC_TID (*((reg32_t *)(EMAC_BASE + EMAC_TID_OFF))) ///< Type ID checking register address.
325 //#define EMAC_TPQ_OFF 0x000000BC ///< Transmit pause quantum register offset.
326 //#define EMAC_TPQ (*((reg32_t *)(EMAC_BASE + EMAC_TPQ_OFF))) ///< Transmit pause quantum register address.
330 * User Input/Output Register
334 #define EMAC_USRIO_OFF 0x000000C0 ///< User input/output register offset.
335 #define EMAC_USRIO (*((reg32_t *)(EMAC_BASE + EMAC_USRIO_OFF))) ///< User input/output register address.
337 #define EMAC_RMII 0 ///< Enable reduced MII.
338 #define EMAC_CLKEN 1 ///< Enable tranceiver input clock.
343 * Wake On LAN Register
347 #define EMAC_WOL_OFF 0x000000C4 ///< Wake On LAN register offset.
348 #define EMAC_WOL (*((reg32_t *)(EMAC_BASE + EMAC_WOL_OFF) ///< Wake On LAN register address.
349 #define EMAC_IP 0x0000FFFF ///< ARP request IP address mask.
350 #define EMAC_MAG 0x00010000 ///< Magic packet event enable.
351 #define EMAC_ARP 0x00020000 ///< ARP request event enable.
352 #define EMAC_SA1 0x00040000 ///< Specific address register 1 event enable.
355 ** Revision Register *
357 #define EMAC_REV_OFF 0x000000FC ///< Revision register offset.
358 #define EMAC_REV (*((reg32_t *)(EMAC_BASE + EMAC_REV_OFF) ///< Revision register address.
359 #define EMAC_REVREF 0x0000FFFF ///< Revision.
360 #define EMAC_PARTREF 0xFFFF0000 ///< Part.
364 #endif /* AT91_EMAC_H */