4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
35 * \author Francesco Sacchi <batt@develer.com>
37 * AT91 Parallel input/output controller.
38 * This file is based on NUT/OS implementation. See license below.
42 * Copyright (C) 2005-2006 by egnite Software GmbH. All rights reserved.
44 * Redistribution and use in source and binary forms, with or without
45 * modification, are permitted provided that the following conditions
48 * 1. Redistributions of source code must retain the above copyright
49 * notice, this list of conditions and the following disclaimer.
50 * 2. Redistributions in binary form must reproduce the above copyright
51 * notice, this list of conditions and the following disclaimer in the
52 * documentation and/or other materials provided with the distribution.
53 * 3. Neither the name of the copyright holders nor the names of
54 * contributors may be used to endorse or promote products derived
55 * from this software without specific prior written permission.
57 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
58 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
59 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
60 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
61 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
63 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
64 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
65 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
66 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
67 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
70 * For additional information see http://www.ethernut.de/
76 /** PIO Register Offsets */
78 #define PIO_PER_OFF 0x00000000 ///< PIO enable register offset.
79 #define PIO_PDR_OFF 0x00000004 ///< PIO disable register offset.
80 #define PIO_PSR_OFF 0x00000008 ///< PIO status register offset.
81 #define PIO_OER_OFF 0x00000010 ///< Output enable register offset.
82 #define PIO_ODR_OFF 0x00000014 ///< Output disable register offset.
83 #define PIO_OSR_OFF 0x00000018 ///< Output status register offset.
84 #define PIO_IFER_OFF 0x00000020 ///< Input filter enable register offset.
85 #define PIO_IFDR_OFF 0x00000024 ///< Input filter disable register offset.
86 #define PIO_IFSR_OFF 0x00000028 ///< Input filter status register offset.
87 #define PIO_SODR_OFF 0x00000030 ///< Set output data register offset.
88 #define PIO_CODR_OFF 0x00000034 ///< Clear output data register offset.
89 #define PIO_ODSR_OFF 0x00000038 ///< Output data status register offset.
90 #define PIO_PDSR_OFF 0x0000003C ///< Pin data status register offset.
91 #define PIO_IER_OFF 0x00000040 ///< Interrupt enable register offset.
92 #define PIO_IDR_OFF 0x00000044 ///< Interrupt disable register offset.
93 #define PIO_IMR_OFF 0x00000048 ///< Interrupt mask register offset.
94 #define PIO_ISR_OFF 0x0000004C ///< Interrupt status register offset.
95 #if PIO_HAS_MULTIDRIVER
96 #define PIO_MDER_OFF 0x00000050 ///< Multi-driver enable register offset.
97 #define PIO_MDDR_OFF 0x00000054 ///< Multi-driver disable register offset.
98 #define PIO_MDSR_OFF 0x00000058 ///< Multi-driver status register offset.
99 #endif /* PIO_HAS_MULTIDRIVER */
101 #define PIO_PUDR_OFF 0x00000060 ///< Pull-up disable register offset.
102 #define PIO_PUER_OFF 0x00000064 ///< Pull-up enable register offset.
103 #define PIO_PUSR_OFF 0x00000068 ///< Pull-up status register offset.
104 #endif /* PIO_HAS_PULLUP */
105 #if PIO_HAS_PERIPHERALSELECT
106 #define PIO_ASR_OFF 0x00000070 ///< PIO peripheral A select register offset.
107 #define PIO_BSR_OFF 0x00000074 ///< PIO peripheral B select register offset.
108 #define PIO_ABSR_OFF 0x00000078 ///< PIO peripheral AB status register offset.
109 #endif /* PIO_HAS_PERIPHERALSELECT */
110 #if PIO_HAS_OUTPUTWRITEENABLE
111 #define PIO_OWER_OFF 0x000000A0 ///< PIO output write enable register offset.
112 #define PIO_OWDR_OFF 0x000000A4 ///< PIO output write disable register offset.
113 #define PIO_OWSR_OFF 0x000000A8 ///< PIO output write status register offset.
114 #endif /* PIO_HAS_OUTPUTWRITEENABLE */
117 /** Single PIO Register Addresses */
119 #if defined(PIO_BASE)
120 #define PIO_ACCESS(offset) (*((reg32_t *)(PIO_BASE + (offset))))
122 #define PIO_PER PIO_ACCESS(PIO_PER_OFF) ///< PIO enable register address.
123 #define PIO_PDR PIO_ACCESS(PIO_PDR_OFF) ///< PIO disable register address.
124 #define PIO_PSR PIO_ACCESS(PIO_PSR_OFF) ///< PIO status register address.
125 #define PIO_OER PIO_ACCESS(PIO_OER_OFF) ///< Output enable register address.
126 #define PIO_ODR PIO_ACCESS(PIO_ODR_OFF) ///< Output disable register address.
127 #define PIO_OSR PIO_ACCESS(PIO_OSR_OFF) ///< Output status register address.
128 #define PIO_IFER PIO_ACCESS(PIO_IFER_OFF) ///< Input filter enable register address.
129 #define PIO_IFDR PIO_ACCESS(PIO_IFDR_OFF) ///< Input filter disable register address.
130 #define PIO_IFSR PIO_ACCESS(PIO_IFSR_OFF) ///< Input filter status register address.
131 #define PIO_SODR PIO_ACCESS(PIO_SODR_OFF) ///< Set output data register address.
132 #define PIO_CODR PIO_ACCESS(PIO_CODR_OFF) ///< Clear output data register address.
133 #define PIO_ODSR PIO_ACCESS(PIO_ODSR_OFF) ///< Output data status register address.
134 #define PIO_PDSR PIO_ACCESS(PIO_PDSR_OFF) ///< Pin data status register address.
135 #define PIO_IER PIO_ACCESS(PIO_IER_OFF) ///< Interrupt enable register address.
136 #define PIO_IDR PIO_ACCESS(PIO_IDR_OFF) ///< Interrupt disable register address.
137 #define PIO_IMR PIO_ACCESS(PIO_IMR_OFF) ///< Interrupt mask register address.
138 #define PIO_ISR PIO_ACCESS(PIO_ISR_OFF) ///< Interrupt status register address.
139 #if PIO_HAS_MULTIDRIVER
140 #define PIO_MDER PIO_ACCESS(PIO_MDER_OFF) ///< Multi-driver enable register address.
141 #define PIO_MDDR PIO_ACCESS(PIO_MDDR_OFF) ///< Multi-driver disable register address.
142 #define PIO_MDSR PIO_ACCESS(PIO_MDSR_OFF) ///< Multi-driver status register address.
143 #endif /* PIO_HAS_MULTIDRIVER */
145 #define PIO_PUDR PIO_ACCESS(PIO_PUDR_OFF) ///< Pull-up disable register address.
146 #define PIO_PUER PIO_ACCESS(PIO_PUER_OFF) ///< Pull-up enable register address.
147 #define PIO_PUSR PIO_ACCESS(PIO_PUSR_OFF) ///< Pull-up status register address.
148 #endif /* PIO_HAS_PULLUP */
149 #if PIO_HAS_PERIPHERALSELECT
150 #define PIO_ASR PIO_ACCESS(PIO_ASR_OFF) ///< PIO peripheral A select register address.
151 #define PIO_BSR PIO_ACCESS(PIO_BSR_OFF) ///< PIO peripheral B select register address.
152 #define PIO_ABSR PIO_ACCESS(PIO_ABSR_OFF) ///< PIO peripheral AB status register address.
153 #endif /* PIO_HAS_PERIPHERALSELECT */
154 #if PIO_HAS_OUTPUTWRITEENABLE
155 #define PIO_OWER PIO_ACCESS(PIO_OWER_OFF) ///< PIO output write enable register address.
156 #define PIO_OWDR PIO_ACCESS(PIO_OWDR_OFF) ///< PIO output write disable register address.
157 #define PIO_OWSR PIO_ACCESS(PIO_OWSR_OFF) ///< PIO output write status register address.
158 #endif /* PIO_HAS_OUTPUTWRITEENABLE */
159 #endif /* PIO_BASE */
162 /** PIO A Register Addresses */
164 #if defined(PIOA_BASE)
165 #define PIOA_ACCESS(offset) (*((reg32_t *)(PIOA_BASE + (offset))))
167 #define PIOA_PER PIOA_ACCESS(PIO_PER_OFF) ///< PIO enable register address.
168 #define PIOA_PDR PIOA_ACCESS(PIO_PDR_OFF) ///< PIO disable register address.
169 #define PIOA_PSR PIOA_ACCESS(PIO_PSR_OFF) ///< PIO status register address.
170 #define PIOA_OER PIOA_ACCESS(PIO_OER_OFF) ///< Output enable register address.
171 #define PIOA_ODR PIOA_ACCESS(PIO_ODR_OFF) ///< Output disable register address.
172 #define PIOA_OSR PIOA_ACCESS(PIO_OSR_OFF) ///< Output status register address.
173 #define PIOA_IFER PIOA_ACCESS(PIO_IFER_OFF) ///< Input filter enable register address.
174 #define PIOA_IFDR PIOA_ACCESS(PIO_IFDR_OFF) ///< Input filter disable register address.
175 #define PIOA_IFSR PIOA_ACCESS(PIO_IFSR_OFF) ///< Input filter status register address.
176 #define PIOA_SODR PIOA_ACCESS(PIO_SODR_OFF) ///< Set output data register address.
177 #define PIOA_CODR PIOA_ACCESS(PIO_CODR_OFF) ///< Clear output data register address.
178 #define PIOA_ODSR PIOA_ACCESS(PIO_ODSR_OFF) ///< Output data status register address.
179 #define PIOA_PDSR PIOA_ACCESS(PIO_PDSR_OFF) ///< Pin data status register address.
180 #define PIOA_IER PIOA_ACCESS(PIO_IER_OFF) ///< Interrupt enable register address.
181 #define PIOA_IDR PIOA_ACCESS(PIO_IDR_OFF) ///< Interrupt disable register address.
182 #define PIOA_IMR PIOA_ACCESS(PIO_IMR_OFF) ///< Interrupt mask register address.
183 #define PIOA_ISR PIOA_ACCESS(PIO_ISR_OFF) ///< Interrupt status register address.
184 #if PIO_HAS_MULTIDRIVER
185 #define PIOA_MDER PIOA_ACCESS(PIO_MDER_OFF) ///< Multi-driver enable register address.
186 #define PIOA_MDDR PIOA_ACCESS(PIO_MDDR_OFF) ///< Multi-driver disable register address.
187 #define PIOA_MDSR PIOA_ACCESS(PIO_MDSR_OFF) ///< Multi-driver status register address.
188 #endif /* PIO_HAS_MULTIDRIVER */
190 #define PIOA_PUDR PIOA_ACCESS(PIO_PUDR_OFF) ///< Pull-up disable register address.
191 #define PIOA_PUER PIOA_ACCESS(PIO_PUER_OFF) ///< Pull-up enable register address.
192 #define PIOA_PUSR PIOA_ACCESS(PIO_PUSR_OFF) ///< Pull-up status register address.
193 #endif /* PIO_HAS_PULLUP */
194 #if PIO_HAS_PERIPHERALSELECT
195 #define PIOA_ASR PIOA_ACCESS(PIO_ASR_OFF) ///< PIO peripheral A select register address.
196 #define PIOA_BSR PIOA_ACCESS(PIO_BSR_OFF) ///< PIO peripheral B select register address.
197 #define PIOA_ABSR PIOA_ACCESS(PIO_ABSR_OFF) ///< PIO peripheral AB status register address.
198 #endif /* PIO_HAS_PERIPHERALSELECT */
199 #if PIO_HAS_OUTPUTWRITEENABLE
200 #define PIOA_OWER PIOA_ACCESS(PIO_OWER_OFF) ///< PIO output write enable register address.
201 #define PIOA_OWDR PIOA_ACCESS(PIO_OWDR_OFF) ///< PIO output write disable register address.
202 #define PIOA_OWSR PIOA_ACCESS(PIO_OWSR_OFF) ///< PIO output write status register address.
203 #endif /* PIO_HAS_OUTPUTWRITEENABLE */
204 #endif /* PIOA_BASE */
207 /** PIO B Register Addresses */
209 #if defined(PIOB_BASE)
210 #define PIOB_ACCESS(offset) (*((reg32_t *)(PIOB_BASE + (offset))))
212 #define PIOB_PER PIOB_ACCESS(PIO_PER_OFF) ///< PIO enable register address.
213 #define PIOB_PDR PIOB_ACCESS(PIO_PDR_OFF) ///< PIO disable register address.
214 #define PIOB_PSR PIOB_ACCESS(PIO_PSR_OFF) ///< PIO status register address.
215 #define PIOB_OER PIOB_ACCESS(PIO_OER_OFF) ///< Output enable register address.
216 #define PIOB_ODR PIOB_ACCESS(PIO_ODR_OFF) ///< Output disable register address.
217 #define PIOB_OSR PIOB_ACCESS(PIO_OSR_OFF) ///< Output status register address.
218 #define PIOB_IFER PIOB_ACCESS(PIO_IFER_OFF) ///< Input filter enable register address.
219 #define PIOB_IFDR PIOB_ACCESS(PIO_IFDR_OFF) ///< Input filter disable register address.
220 #define PIOB_IFSR PIOB_ACCESS(PIO_IFSR_OFF) ///< Input filter status register address.
221 #define PIOB_SODR PIOB_ACCESS(PIO_SODR_OFF) ///< Set output data register address.
222 #define PIOB_CODR PIOB_ACCESS(PIO_CODR_OFF) ///< Clear output data register address.
223 #define PIOB_ODSR PIOB_ACCESS(PIO_ODSR_OFF) ///< Output data status register address.
224 #define PIOB_PDSR PIOB_ACCESS(PIO_PDSR_OFF) ///< Pin data status register address.
225 #define PIOB_IER PIOB_ACCESS(PIO_IER_OFF) ///< Interrupt enable register address.
226 #define PIOB_IDR PIOB_ACCESS(PIO_IDR_OFF) ///< Interrupt disable register address.
227 #define PIOB_IMR PIOB_ACCESS(PIO_IMR_OFF) ///< Interrupt mask register address.
228 #define PIOB_ISR PIOB_ACCESS(PIO_ISR_OFF) ///< Interrupt status register address.
229 #if PIO_HAS_MULTIDRIVER
230 #define PIOB_MDER PIOB_ACCESS(PIO_MDER_OFF) ///< Multi-driver enable register address.
231 #define PIOB_MDDR PIOB_ACCESS(PIO_MDDR_OFF) ///< Multi-driver disable register address.
232 #define PIOB_MDSR PIOB_ACCESS(PIO_MDSR_OFF) ///< Multi-driver status register address.
233 #endif /* PIO_HAS_MULTIDRIVER */
235 #define PIOB_PUDR PIOB_ACCESS(PIO_PUDR_OFF) ///< Pull-up disable register address.
236 #define PIOB_PUER PIOB_ACCESS(PIO_PUER_OFF) ///< Pull-up enable register address.
237 #define PIOB_PUSR PIOB_ACCESS(PIO_PUSR_OFF) ///< Pull-up status register address.
238 #endif /* PIO_HAS_PULLUP */
239 #if PIO_HAS_PERIPHERALSELECT
240 #define PIOB_ASR PIOB_ACCESS(PIO_ASR_OFF) ///< PIO peripheral A select register address.
241 #define PIOB_BSR PIOB_ACCESS(PIO_BSR_OFF) ///< PIO peripheral B select register address.
242 #define PIOB_ABSR PIOB_ACCESS(PIO_ABSR_OFF) ///< PIO peripheral AB status register address.
243 #endif /* PIO_HAS_PERIPHERALSELECT */
244 #if PIO_HAS_OUTPUTWRITEENABLE
245 #define PIOB_OWER PIOB_ACCESS(PIO_OWER_OFF) ///< PIO output write enable register address.
246 #define PIOB_OWDR PIOB_ACCESS(PIO_OWDR_OFF) ///< PIO output write disable register address.
247 #define PIOB_OWSR PIOB_ACCESS(PIO_OWSR_OFF) ///< PIO output write status register address.
248 #endif /* PIO_HAS_OUTPUTWRITEENABLE */
249 #endif /* PIOB_BASE */
252 /** PIO C Register Addresses */
254 #if defined(PIOC_BASE)
255 #define PIOC_ACCESS(offset) (*((reg32_t *)(PIOC_BASE + (offset))))
257 #define PIOC_PER PIOC_ACCESS(PIO_PER_OFF) ///< PIO enable register address.
258 #define PIOC_PDR PIOC_ACCESS(PIO_PDR_OFF) ///< PIO disable register address.
259 #define PIOC_PSR PIOC_ACCESS(PIO_PSR_OFF) ///< PIO status register address.
260 #define PIOC_OER PIOC_ACCESS(PIO_OER_OFF) ///< Output enable register address.
261 #define PIOC_ODR PIOC_ACCESS(PIO_ODR_OFF) ///< Output disable register address.
262 #define PIOC_OSR PIOC_ACCESS(PIO_OSR_OFF) ///< Output status register address.
263 #define PIOC_IFER PIOC_ACCESS(PIO_IFER_OFF) ///< Input filter enable register address.
264 #define PIOC_IFDR PIOC_ACCESS(PIO_IFDR_OFF) ///< Input filter disable register address.
265 #define PIOC_IFSR PIOC_ACCESS(PIO_IFSR_OFF) ///< Input filter status register address.
266 #define PIOC_SODR PIOC_ACCESS(PIO_SODR_OFF) ///< Set output data register address.
267 #define PIOC_CODR PIOC_ACCESS(PIO_CODR_OFF) ///< Clear output data register address.
268 #define PIOC_ODSR PIOC_ACCESS(PIO_ODSR_OFF) ///< Output data status register address.
269 #define PIOC_PDSR PIOC_ACCESS(PIO_PDSR_OFF) ///< Pin data status register address.
270 #define PIOC_IER PIOC_ACCESS(PIO_IER_OFF) ///< Interrupt enable register address.
271 #define PIOC_IDR PIOC_ACCESS(PIO_IDR_OFF) ///< Interrupt disable register address.
272 #define PIOC_IMR PIOC_ACCESS(PIO_IMR_OFF) ///< Interrupt mask register address.
273 #define PIOC_ISR PIOC_ACCESS(PIO_ISR_OFF) ///< Interrupt status register address.
274 #if PIO_HAS_MULTIDRIVER
275 #define PIOC_MDER PIOC_ACCESS(PIO_MDER_OFF) ///< Multi-driver enable register address.
276 #define PIOC_MDDR PIOC_ACCESS(PIO_MDDR_OFF) ///< Multi-driver disable register address.
277 #define PIOC_MDSR PIOC_ACCESS(PIO_MDSR_OFF) ///< Multi-driver status register address.
278 #endif /* PIO_HAS_MULTIDRIVER */
280 #define PIOC_PUDR PIOC_ACCESS(PIO_PUDR_OFF) ///< Pull-up disable register address.
281 #define PIOC_PUER PIOC_ACCESS(PIO_PUER_OFF) ///< Pull-up enable register address.
282 #define PIOC_PUSR PIOC_ACCESS(PIO_PUSR_OFF) ///< Pull-up status register address.
283 #endif /* PIO_HAS_PULLUP */
284 #if PIO_HAS_PERIPHERALSELECT
285 #define PIOC_ASR PIOC_ACCESS(PIO_ASR_OFF) ///< PIO peripheral A select register address.
286 #define PIOC_BSR PIOC_ACCESS(PIO_BSR_OFF) ///< PIO peripheral B select register address.
287 #define PIOC_ABSR PIOC_ACCESS(PIO_ABSR_OFF) ///< PIO peripheral AB status register address.
288 #endif /* PIO_HAS_PERIPHERALSELECT */
289 #if PIO_HAS_OUTPUTWRITEENABLE
290 #define PIOC_OWER PIOC_ACCESS(PIO_OWER_OFF) ///< PIO output write enable register address.
291 #define PIOC_OWDR PIOC_ACCESS(PIO_OWDR_OFF) ///< PIO output write disable register address.
292 #define PIOC_OWSR PIOC_ACCESS(PIO_OWSR_OFF) ///< PIO output write status register address.
293 #endif /* PIO_HAS_OUTPUTWRITEENABLE */
294 #endif /* PIOC_BASE */
297 #endif /* AT91_PIO_H */