4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2008 Develer S.r.l. (http://www.develer.com/)
35 * \author Francesco Sacchi <batt@develer.com>
37 * AT91SAM7 Two wire interface.
38 * This file is based on NUT/OS implementation. See license below.
42 * Copyright (C) 2006 by egnite Software GmbH. All rights reserved.
44 * Redistribution and use in source and binary forms, with or without
45 * modification, are permitted provided that the following conditions
48 * 1. Redistributions of source code must retain the above copyright
49 * notice, this list of conditions and the following disclaimer.
50 * 2. Redistributions in binary form must reproduce the above copyright
51 * notice, this list of conditions and the following disclaimer in the
52 * documentation and/or other materials provided with the distribution.
53 * 3. Neither the name of the copyright holders nor the names of
54 * contributors may be used to endorse or promote products derived
55 * from this software without specific prior written permission.
57 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
58 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
59 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
60 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
61 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
62 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
63 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
64 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
65 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
66 * OR TORT (*((reg32_t *)(INCLUDING NEGLIGENCE OR OTHERWISE))) ARISING IN ANY WAY OUT OF
67 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
70 * For additional information see http://www.ethernut.de/
78 * TWI Control Register.
81 #define TWI_CR_OFF 0x00000000 ///< Control register offset.
82 #define TWI_CR (*((reg32_t *)(TWI_BASE + TWI_CR_OFF))) ///< Control register address.
83 #define TWI_START 0 ///< Send start condition.
84 #define TWI_STOP 1 ///< Send stop condition.
85 #define TWI_MSEN 2 ///< Enable master mode.
86 #define TWI_MSDIS 3 ///< Disable master mode.
88 #define TWI_SVEN 4 ///< Enable slave mode.
89 #define TWI_SVDIS 5 ///< Disable slave mode.
91 #define TWI_SWRST 7 ///< Software reset.
95 * TWI Master Mode Register.
98 #define TWI_MMR_OFF 0x00000004 ///< Master mode register offset.
99 #define TWI_MMR (*((reg32_t *)(TWI_BASE + TWI_MMR_OFF))) ///< Master mode register address.
100 #define TWI_IADRSZ_SHIFT 8 ///< Internal device address size shift.
101 #define TWI_IADRSZ 0x00000300 ///< Internal device address size mask.
102 #define TWI_IADRSZ_NONE 0x00000000 ///< No internal device address.
103 #define TWI_IADRSZ_1BYTE 0x00000100 ///< One byte internal device address.
104 #define TWI_IADRSZ_2BYTE 0x00000200 ///< Two byte internal device address.
105 #define TWI_IADRSZ_3BYTE 0x00000300 ///< Three byte internal device address.
106 #define TWI_MREAD 12 ///< Master read direction.
107 #define TWI_DADR 0x007F0000 ///< Device address mask.
108 #define TWI_DADR_SHIFT 16 ///< Device address LSB.
112 * TWI Internal Address Register.
115 #define TWI_IADR_OFF 0x0000000C ///< Internal address register offset.
116 #define TWI_IADR (*((reg32_t *)(TWI_BASE + TWI_IADR_OFF))) ///< Internal address register address.
117 #define TWI_IADR_MASK 0x00FFFFFF ///< Internal address mask.
118 #define TWI_IADR_SHIFT 0 ///< Internal address LSB.
122 * TWI Clock Waveform Generator Register.
125 #define TWI_CWGR_OFF 0x00000010 ///< Clock waveform generator register offset.
126 #define TWI_CWGR (*((reg32_t *)(TWI_BASE + TWI_CWGR_OFF))) ///< Clock waveform generator register address.
127 #define TWI_CLDIV 0x000000FF ///< Clock low divider mask.
128 #define TWI_CLDIV_SHIFT 0 ///< Clock low divider LSB.
129 #define TWI_CHDIV 0x0000FF00 ///< Clock high divider mask.
130 #define TWI_CHDIV_SHIFT 8 ///< Clock high divider LSB.
131 #define TWI_CKDIV 0x00070000 ///< Clock divider mask.
132 #define TWI_CKDIV_SHIFT 16 ///< Clock divider LSB.
136 * TWI Status and Interrupt Registers.
139 #define TWI_SR_OFF 0x00000020 ///< Status register offset.
140 #define TWI_SR (*((reg32_t *)(TWI_BASE + TWI_SR_OFF))) ///< Status register address.
142 #define TWI_IER_OFF 0x00000024 ///< Interrupt enable register offset.
143 #define TWI_IER (*((reg32_t *)(TWI_BASE + TWI_IER_OFF))) ///< Interrupt enable register address.
145 #define TWI_IDR_OFF 0x00000028 ///< Interrupt disable register offset.
146 #define TWI_IDR (*((reg32_t *)(TWI_BASE + TWI_IDR_OFF))) ///< Interrupt disable register address.
148 #define TWI_IMR_OFF 0x0000002C ///< Interrupt mask register offset.
149 #define TWI_IMR (*((reg32_t *)(TWI_BASE + TWI_IMR_OFF))) ///< Interrupt mask register address.
151 #define TWI_TXCOMP 0 ///< Transmission completed.
152 #define TWI_RXRDY 1 ///< Receive holding register ready.
153 #define TWI_TXRDY 2 ///< Transmit holding register ready.
156 #define TWI_SVREAD 0x00000008 ///< Slave read.
157 #define TWI_SVACC 0x00000010 ///< Slave access.
158 #define TWI_GACC 0x00000020 ///< General call access.
161 #if CPU_ARM_AT91SAM7X256 || CPU_ARM_AT91SAM7X128
162 #define TWI_OVRE 6 ///< Overrun error.
163 #define TWI_UNRE 7 ///< Underrun error.
166 #define TWI_NACK 8 ///< Not acknowledged.
168 #define TWI_ARBLST 0x00000200 ///< Arbitration lost.
169 #define TWI_SCLWS 0x00000400 ///< Clock wait state.
170 #define TWI_EOSACC 0x00000800 ///< End of slave access.
175 * TWI Receive Holding Register.
178 #define TWI_RHR_OFF 0x00000030 ///< Receive holding register offset.
179 #define TWI_RHR (*((reg32_t *)(TWI_BASE + TWI_RHR_OFF))) ///< Receive holding register address.
183 * TWI Transmit Holding Register.
186 #define TWI_THR_OFF 0x00000034 ///< Transmit holding register offset.
187 #define TWI_THR (*((reg32_t *)(TWI_BASE + TWI_THR_OFF))) ///< Transmit holding register address.
191 #endif /* AT91_TWI_H */