4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
35 * \author Francesco Sacchi <batt@develer.com>
36 * \author Daniele Basile <asterix@develer.com>
38 * AT91SAM7 register definitions.
39 * This file is based on NUT/OS implementation. See license below.
43 * Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
45 * Redistribution and use in source and binary forms, with or without
46 * modification, are permitted provided that the following conditions
49 * 1. Redistributions of source code must retain the above copyright
50 * notice, this list of conditions and the following disclaimer.
51 * 2. Redistributions in binary form must reproduce the above copyright
52 * notice, this list of conditions and the following disclaimer in the
53 * documentation and/or other materials provided with the distribution.
54 * 3. Neither the name of the copyright holders nor the names of
55 * contributors may be used to endorse or promote products derived
56 * from this software without specific prior written permission.
58 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
59 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
60 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
61 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL EGNITE
62 * SOFTWARE GMBH OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
64 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
65 * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
66 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
67 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
68 * THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
71 * For additional information see http://www.ethernut.de/
77 #include <cfg/compiler.h>
79 #if CPU_ARM_SAM7X || CPU_ARM_SAM7S_LARGE
80 #define FLASH_BASE 0x100000UL
81 #define RAM_BASE 0x200000UL
83 #define TC_BASE 0xFFFA0000 ///< Timer/counter base address.
84 #define UDP_BASE 0xFFFB0000 ///< USB device port base address.
85 #define TWI_BASE 0xFFFB8000 ///< Two-wire interface base address.
86 #define USART0_BASE 0xFFFC0000 ///< USART 0 base address.
87 #define USART1_BASE 0xFFFC4000 ///< USART 1 base address.
88 #define PWMC_BASE 0xFFFCC000 ///< PWM controller base address.
89 #define SSC_BASE 0xFFFD4000 ///< Serial synchronous controller base address.
90 #define ADC_BASE 0xFFFD8000 ///< ADC base address.
92 #define AIC_BASE 0xFFFFF000 ///< AIC base address.
93 #define DBGU_BASE 0xFFFFF200 ///< DBGU base address.
94 #define PIOA_BASE 0xFFFFF400 ///< PIO A base address.
95 #define PMC_BASE 0xFFFFFC00 ///< PMC base address.
96 #define RSTC_BASE 0xFFFFFD00 ///< Resect controller register base address.
97 #define RTT_BASE 0xFFFFFD20 ///< Realtime timer base address.
98 #define PIT_BASE 0xFFFFFD30 ///< Periodic interval timer base address.
99 #define WDT_BASE 0xFFFFFD40 ///< Watch Dog register base address.
100 #define VREG_BASE 0xFFFFFD60 ///< Voltage regulator mode controller base address.
101 #define MC_BASE 0xFFFFFF00 ///< Memory controller base.
104 #define CAN_BASE 0xFFFD0000 ///< PWM controller base address.
105 #define EMAC_BASE 0xFFFDC000 ///< Ethernet MAC address.
106 #define SPI0_BASE 0xFFFE0000 ///< SPI0 base address.
107 #define SPI1_BASE 0xFFFE4000 ///< SPI1 base address.
108 #define PIOB_BASE 0xFFFFF600 ///< PIO base address.
111 #if CPU_ARM_SAM7S_LARGE
112 #define SPI_BASE 0xFFFE0000 ///< SPI0 base address.
115 #define PIO_HAS_MULTIDRIVER 1
116 #define PIO_HAS_PULLUP 1
117 #define PIO_HAS_PERIPHERALSELECT 1
118 #define PIO_HAS_OUTPUTWRITEENABLE 1
120 #define DBGU_HAS_PDC 1
121 #define SPI_HAS_PDC 1
122 #define SSC_HAS_PDC 1
123 #define USART_HAS_PDC 1
126 #define PERIPH_RPR_OFF 0x100 ///< Receive Pointer Register.
127 #define PERIPH_RCR_OFF 0x104 ///< Receive Counter Register.
128 #define PERIPH_TPR_OFF 0x108 ///< Transmit Pointer Register.
129 #define PERIPH_TCR_OFF 0x10C ///< Transmit Counter Register.
130 #define PERIPH_RNPR_OFF 0x110 ///< Receive Next Pointer Register.
131 #define PERIPH_RNCR_OFF 0x114 ///< Receive Next Counter Register.
132 #define PERIPH_TNPR_OFF 0x118 ///< Transmit Next Pointer Register.
133 #define PERIPH_TNCR_OFF 0x11C ///< Transmit Next Counter Register.
134 #define PERIPH_PTCR_OFF 0x120 ///< PDC Transfer Control Register.
135 #define PERIPH_PTSR_OFF 0x124 ///< PDC Transfer Status Register.
143 #error No base address register definition for selected ARM CPU
147 #if CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X256
148 #define FLASH_MEM_SIZE 0x40000UL ///< Internal flash memory size
149 #define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes
150 #define FLASH_BANKS_NUM 1 ///< Number of flash banks
151 #define FLASH_SECTORS_NUM 16 ///< Number of flash sector
152 #define FLASH_PAGE_PER_SECTOR 64 ///< Number of page for sector
155 #error Memory size definition for selected ARM CPU
158 #include "at91_aic.h"
159 #include "at91_pit.h"
160 #include "at91_pmc.h"
162 #include "at91_wdt.h"
163 #include "at91_rstc.h"
164 #include "at91_pio.h"
166 #include "at91_dbgu.h"
168 #include "at91_adc.h"
169 #include "at91_pwm.h"
170 #include "at91_spi.h"
171 #include "at91_twi.h"
172 #include "at91_ssc.h"
173 //TODO: add other peripherals
176 * Peripheral Identifiers and Interrupts
179 #if CPU_ARM_SAM7X || CPU_ARM_SAM7S_LARGE
180 #define FIQ_ID 0 ///< Fast interrupt ID.
181 #define SYSC_ID 1 ///< System controller interrupt.
182 #define US0_ID 6 ///< USART 0 ID.
183 #define US1_ID 7 ///< USART 1 ID.
184 #define SSC_ID 8 ///< Synchronous serial controller ID.
185 #define TWI_ID 9 ///< Two-wire interface ID.
186 #define PWMC_ID 10 ///< PWM controller ID.
187 #define UDP_ID 11 ///< USB device port ID.
188 #define TC0_ID 12 ///< Timer 0 ID.
189 #define TC1_ID 13 ///< Timer 1 ID.
190 #define TC2_ID 14 ///< Timer 2 ID.
192 #define IRQ0_ID 30 ///< External interrupt 0 ID.
193 #define IRQ1_ID 31 ///< External interrupt 1 ID.
196 #define PIOA_ID 2 ///< Parallel A I/O controller ID.
197 #define PIOB_ID 3 ///< Parallel B I/O controller ID.
198 #define SPI0_ID 4 ///< Serial peripheral interface 0 ID.
199 #define SPI1_ID 5 ///< Serial peripheral interface 1 ID.
200 #define CAN_ID 15 ///< CAN controller ID.
201 #define EMAC_ID 16 ///< Ethernet MAC ID.
202 #define ADC_ID 17 ///< Analog to digital converter ID.
207 #if CPU_ARM_SAM7S_LARGE
208 #define PIOA_ID 2 ///< Parallel I/O controller ID.
209 /* ID 3 is reserved */
210 #define ADC_ID 4 ///< Analog to digital converter ID.
211 #define SPI_ID 5 ///< Serial peripheral interface ID.
212 #define SPI0_ID SPI_ID ///< Alias
216 #error No peripheral ID and interrupts definition for selected ARM CPU
222 * USART & DEBUG pin names
225 #if CPU_ARM_SAM7S_LARGE
233 #define RXD0 0 // PA0
234 #define TXD0 1 // PA1
235 #define RXD1 5 // PA5
236 #define TXD1 6 // PA6
237 #define DTXD 28 // PA28
238 #define DRXD 27 // PA27
240 #error No USART & debug pin names definition for selected ARM CPU
248 #if CPU_ARM_SAM7S_LARGE
249 #define SPI0_NPCS0 11 // Same as NSS pin.
255 #define SPI0_NPCS0 12 // Same as NSS pin. PA12
256 #define SPI0_NPCS1 13 // PA13
257 #define SPI0_NPCS2 14 // PA14
258 #define SPI0_NPCS3 15 // PA15
259 #define SPI0_MISO 16 // PA16
260 #define SPI0_MOSI 17 // PA17
261 #define SPI0_SPCK 18 // PA18
263 #define SPI1_NPCS0 21 // Same as NSS pin. PA21
264 #define SPI1_NPCS1 25 // PA25
265 #define SPI1_NPCS2 26 // PA26
266 #define SPI1_NPCS3 29 // PA29
267 #define SPI1_MISO 24 // PA24
268 #define SPI1_MOSI 23 // PA23
269 #define SPI1_SPCK 22 // PA22
272 #error No SPI pins name definition for selected ARM CPU
281 #if CPU_ARM_SAM7S_LARGE
283 #define SSC_TF 15 // PA15
284 #define SSC_TK 16 // PA16
285 #define SSC_TD 17 // PA17
286 #define SSC_RD 18 // PA18
287 #define SSC_RK 19 // PA19
288 #define SSC_RF 20 // PA20
292 #define SSC_TF 21 // PA21
293 #define SSC_TK 22 // PA22
294 #define SSC_TD 23 // PA23
295 #define SSC_RD 24 // PA24
296 #define SSC_RK 25 // PA25
297 #define SSC_RF 26 // PA26
300 #error No SSC pins name definition for selected ARM CPU
306 * Timer counter pins definition.
310 #define TIOA0 23 // PB23
311 #define TIOB0 24 // PB24
312 #define TIOA1 25 // PB25
313 #define TIOB1 26 // PB26
314 #define TIOA2 27 // PB27
315 #define TIOB2 28 // PB28
317 #define TIO_PIO_PDR PIOB_PDR
318 #define TIO_PIO_ABSR PIOB_ASR
320 #elif CPU_ARM_SAM7S_LARGE
321 #define TIOA0 0 // PA0
322 #define TIOB0 1 // PA1
323 #define TIOA1 15 // PA15
324 #define TIOB1 16 // PA16
325 #define TIOA2 26 // PA26
326 #define TIOB2 27 // PA27
328 #define TIO_PIO_PDR PIOA_PDR
329 #define TIO_PIO_ABSR PIOA_BSR
332 #error No Timer Counter names of pins definition for selected ARM CPU
339 * PWM pins definition.
343 #define PWM0 19 // PB19
344 #define PWM1 20 // PB20
345 #define PWM2 21 // PB21
346 #define PWM3 22 // PB22
348 #define PWM_PIO_PDR PIOB_PDR
349 #define PWM_PIO_PER PIOB_PER
350 #define PWM_PIO_CODR PIOB_CODR
351 #define PWM_PIO_OER PIOB_OER
352 #define PWM_PIO_ABSR PIOB_ASR
354 #elif CPU_ARM_SAM7S_LARGE
355 #define PWM0 11 // PA11
356 #define PWM1 12 // PA12
357 #define PWM2 13 // PA13
358 #define PWM3 14 // PA14
360 #define PWM_PIO_PDR PIOA_PDR
361 #define PWM_PIO_PER PIOA_PER
362 #define PWM_PIO_CODR PIOA_CODR
363 #define PWM_PIO_OER PIOA_OER
364 #define PWM_PIO_ABSR PIOA_BSR
367 #error No PWM names of pins definition for selected ARM CPU
373 * TWI pins definition.
380 #elif CPU_ARM_SAM7S_LARGE
385 #error No TWI names of pins definition for selected ARM CPU
389 * ADC pins definition.
393 #define ADTRG 18 // PB18
394 #define AD0 23 // PB27
395 #define AD1 24 // PB28
396 #define AD2 25 // PB29
397 #define AD3 26 // PB30
399 #elif CPU_ARM_SAM7S_LARGE
400 #define ADTRG 18 // PA8
401 #define AD0 0 // PA17
402 #define AD1 1 // PA18
403 #define AD2 15 // PA19
404 #define AD3 16 // PA20
407 #error No ADC names of pins definition for selected ARM CPU
412 #endif /* AT91SAM7_H */