4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
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24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2007 Develer S.r.l. (http://www.develer.com/)
35 * \author Francesco Sacchi <batt@develer.com>
36 * \author Daniele Basile <asterix@develer.com>
38 * AT91SAM7 register definitions.
39 * This file is based on NUT/OS implementation. See license below.
43 * Copyright (C) 2006-2007 by egnite Software GmbH. All rights reserved.
45 * Redistribution and use in source and binary forms, with or without
46 * modification, are permitted provided that the following conditions
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58 * THIS SOFTWARE IS PROVIDED BY EGNITE SOFTWARE GMBH AND CONTRIBUTORS
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71 * For additional information see http://www.ethernut.de/
77 #include <cfg/compiler.h>
79 #if CPU_ARM_SAM7X || CPU_ARM_SAM7S_LARGE
80 #define FLASH_BASE 0x100000UL
81 #define RAM_BASE 0x200000UL
83 #define TC_BASE 0xFFFA0000 ///< Timer/counter base address.
84 #define UDP_BASE 0xFFFB0000 ///< USB device port base address.
85 #define TWI_BASE 0xFFFB8000 ///< Two-wire interface base address.
86 #define USART0_BASE 0xFFFC0000 ///< USART 0 base address.
87 #define USART1_BASE 0xFFFC4000 ///< USART 1 base address.
88 #define PWMC_BASE 0xFFFCC000 ///< PWM controller base address.
89 #define SSC_BASE 0xFFFD4000 ///< Serial synchronous controller base address.
90 #define ADC_BASE 0xFFFD8000 ///< ADC base address.
92 #define AIC_BASE 0xFFFFF000 ///< AIC base address.
93 #define DBGU_BASE 0xFFFFF200 ///< DBGU base address.
94 #define PIOA_BASE 0xFFFFF400 ///< PIO A base address.
95 #define PMC_BASE 0xFFFFFC00 ///< PMC base address.
96 #define RSTC_BASE 0xFFFFFD00 ///< Resect controller register base address.
97 #define RTT_BASE 0xFFFFFD20 ///< Realtime timer base address.
98 #define PIT_BASE 0xFFFFFD30 ///< Periodic interval timer base address.
99 #define WDT_BASE 0xFFFFFD40 ///< Watch Dog register base address.
100 #define VREG_BASE 0xFFFFFD60 ///< Voltage regulator mode controller base address.
101 #define MC_BASE 0xFFFFFF00 ///< Memory controller base.
104 #define CAN_BASE 0xFFFD0000 ///< PWM controller base address.
105 #define EMAC_BASE 0xFFFDC000 ///< Ethernet MAC address.
106 #define SPI0_BASE 0xFFFE0000 ///< SPI0 base address.
107 #define SPI1_BASE 0xFFFE4000 ///< SPI1 base address.
108 #define PIOB_BASE 0xFFFFF600 ///< PIO base address.
111 #if CPU_ARM_SAM7S_LARGE
112 #define SPI_BASE 0xFFFE0000 ///< SPI0 base address.
115 #define PIO_HAS_MULTIDRIVER 1
116 #define PIO_HAS_PULLUP 1
117 #define PIO_HAS_PERIPHERALSELECT 1
118 #define PIO_HAS_OUTPUTWRITEENABLE 1
120 #define DBGU_HAS_PDC 1
121 #define SPI_HAS_PDC 1
122 #define SSC_HAS_PDC 1
123 #define USART_HAS_PDC 1
126 #define PERIPH_RPR_OFF 0x100 ///< Receive Pointer Register.
127 #define PERIPH_RCR_OFF 0x104 ///< Receive Counter Register.
128 #define PERIPH_TPR_OFF 0x108 ///< Transmit Pointer Register.
129 #define PERIPH_TCR_OFF 0x10C ///< Transmit Counter Register.
130 #define PERIPH_RNPR_OFF 0x110 ///< Receive Next Pointer Register.
131 #define PERIPH_RNCR_OFF 0x114 ///< Receive Next Counter Register.
132 #define PERIPH_TNPR_OFF 0x118 ///< Transmit Next Pointer Register.
133 #define PERIPH_TNCR_OFF 0x11C ///< Transmit Next Counter Register.
134 #define PERIPH_PTCR_OFF 0x120 ///< PDC Transfer Control Register.
135 #define PERIPH_PTSR_OFF 0x124 ///< PDC Transfer Status Register.
143 #error No base address register definition for selected ARM CPU
147 #if CPU_ARM_AT91SAM7S64
148 #define FLASH_MEM_SIZE 0x10000UL ///< Internal flash memory size
149 #define FLASH_PAGE_SIZE_BYTES 128 ///< Size of cpu flash memory page in bytes
150 #define FLASH_BANKS_NUM 1 ///< Number of flash banks
151 #define FLASH_SECTORS_NUM 16 ///< Number of flash sector
152 #define FLASH_PAGE_PER_SECTOR 32 ///< Number of page for sector
154 #elif CPU_ARM_AT91SAM7S128 || CPU_ARM_AT91SAM7X128
155 #define FLASH_MEM_SIZE 0x20000UL ///< Internal flash memory size
156 #define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes
157 #define FLASH_BANKS_NUM 1 ///< Number of flash banks
158 #define FLASH_SECTORS_NUM 8 ///< Number of flash sector
159 #define FLASH_PAGE_PER_SECTOR 64 ///< Number of page for sector
161 #elif CPU_ARM_AT91SAM7S256 || CPU_ARM_AT91SAM7X256
162 #define FLASH_MEM_SIZE 0x40000UL ///< Internal flash memory size
163 #define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes
164 #define FLASH_BANKS_NUM 1 ///< Number of flash banks
165 #define FLASH_SECTORS_NUM 16 ///< Number of flash sector
166 #define FLASH_PAGE_PER_SECTOR 64 ///< Number of page for sector
168 #elif CPU_ARM_AT91SAM7S512 || CPU_ARM_AT91SAM7X512
169 #define FLASH_MEM_SIZE 0x80000UL ///< Internal flash memory size
170 #define FLASH_PAGE_SIZE_BYTES 256 ///< Size of cpu flash memory page in bytes
171 #define FLASH_BANKS_NUM 2 ///< Number of flash banks
172 #define FLASH_SECTORS_NUM 32 ///< Number of flash sector
173 #define FLASH_PAGE_PER_SECTOR 64 ///< Number of page for sector
176 #error Memory size definition for selected ARM CPU
179 #include "at91_aic.h"
180 #include "at91_pit.h"
181 #include "at91_pmc.h"
183 #include "at91_wdt.h"
184 #include "at91_rstc.h"
185 #include "at91_pio.h"
187 #include "at91_dbgu.h"
189 #include "at91_adc.h"
190 #include "at91_pwm.h"
191 #include "at91_spi.h"
192 #include "at91_twi.h"
193 #include "at91_ssc.h"
194 //TODO: add other peripherals
197 * Peripheral Identifiers and Interrupts
200 #if CPU_ARM_SAM7X || CPU_ARM_SAM7S_LARGE
201 #define FIQ_ID 0 ///< Fast interrupt ID.
202 #define SYSC_ID 1 ///< System controller interrupt.
203 #define US0_ID 6 ///< USART 0 ID.
204 #define US1_ID 7 ///< USART 1 ID.
205 #define SSC_ID 8 ///< Synchronous serial controller ID.
206 #define TWI_ID 9 ///< Two-wire interface ID.
207 #define PWMC_ID 10 ///< PWM controller ID.
208 #define UDP_ID 11 ///< USB device port ID.
209 #define TC0_ID 12 ///< Timer 0 ID.
210 #define TC1_ID 13 ///< Timer 1 ID.
211 #define TC2_ID 14 ///< Timer 2 ID.
213 #define IRQ0_ID 30 ///< External interrupt 0 ID.
214 #define IRQ1_ID 31 ///< External interrupt 1 ID.
217 #define PIOA_ID 2 ///< Parallel A I/O controller ID.
218 #define PIOB_ID 3 ///< Parallel B I/O controller ID.
219 #define SPI0_ID 4 ///< Serial peripheral interface 0 ID.
220 #define SPI1_ID 5 ///< Serial peripheral interface 1 ID.
221 #define CAN_ID 15 ///< CAN controller ID.
222 #define EMAC_ID 16 ///< Ethernet MAC ID.
223 #define ADC_ID 17 ///< Analog to digital converter ID.
228 #if CPU_ARM_SAM7S_LARGE
229 #define PIOA_ID 2 ///< Parallel I/O controller ID.
230 /* ID 3 is reserved */
231 #define ADC_ID 4 ///< Analog to digital converter ID.
232 #define SPI_ID 5 ///< Serial peripheral interface ID.
233 #define SPI0_ID SPI_ID ///< Alias
237 #error No peripheral ID and interrupts definition for selected ARM CPU
243 * USART & DEBUG pin names
246 #if CPU_ARM_SAM7S_LARGE
254 #define RXD0 0 // PA0
255 #define TXD0 1 // PA1
256 #define RXD1 5 // PA5
257 #define TXD1 6 // PA6
258 #define DTXD 28 // PA28
259 #define DRXD 27 // PA27
261 #error No USART & debug pin names definition for selected ARM CPU
269 #if CPU_ARM_SAM7S_LARGE
270 #define SPI0_NPCS0 11 // Same as NSS pin.
276 #define SPI0_NPCS0 12 // Same as NSS pin. PA12
277 #define SPI0_NPCS1 13 // PA13
278 #define SPI0_NPCS2 14 // PA14
279 #define SPI0_NPCS3 15 // PA15
280 #define SPI0_MISO 16 // PA16
281 #define SPI0_MOSI 17 // PA17
282 #define SPI0_SPCK 18 // PA18
284 #define SPI1_NPCS0 21 // Same as NSS pin. PA21
285 #define SPI1_NPCS1 25 // PA25
286 #define SPI1_NPCS2 26 // PA26
287 #define SPI1_NPCS3 29 // PA29
288 #define SPI1_MISO 24 // PA24
289 #define SPI1_MOSI 23 // PA23
290 #define SPI1_SPCK 22 // PA22
293 #error No SPI pins name definition for selected ARM CPU
302 #if CPU_ARM_SAM7S_LARGE
304 #define SSC_TF 15 // PA15
305 #define SSC_TK 16 // PA16
306 #define SSC_TD 17 // PA17
307 #define SSC_RD 18 // PA18
308 #define SSC_RK 19 // PA19
309 #define SSC_RF 20 // PA20
313 #define SSC_TF 21 // PA21
314 #define SSC_TK 22 // PA22
315 #define SSC_TD 23 // PA23
316 #define SSC_RD 24 // PA24
317 #define SSC_RK 25 // PA25
318 #define SSC_RF 26 // PA26
321 #error No SSC pins name definition for selected ARM CPU
327 * Timer counter pins definition.
331 #define TIOA0 23 // PB23
332 #define TIOB0 24 // PB24
333 #define TIOA1 25 // PB25
334 #define TIOB1 26 // PB26
335 #define TIOA2 27 // PB27
336 #define TIOB2 28 // PB28
338 #define TIO_PIO_PDR PIOB_PDR
339 #define TIO_PIO_ABSR PIOB_ASR
341 #elif CPU_ARM_SAM7S_LARGE
342 #define TIOA0 0 // PA0
343 #define TIOB0 1 // PA1
344 #define TIOA1 15 // PA15
345 #define TIOB1 16 // PA16
346 #define TIOA2 26 // PA26
347 #define TIOB2 27 // PA27
349 #define TIO_PIO_PDR PIOA_PDR
350 #define TIO_PIO_ABSR PIOA_BSR
353 #error No Timer Counter names of pins definition for selected ARM CPU
360 * PWM pins definition.
364 #define PWM0 19 // PB19
365 #define PWM1 20 // PB20
366 #define PWM2 21 // PB21
367 #define PWM3 22 // PB22
369 #define PWM_PIO_PDR PIOB_PDR
370 #define PWM_PIO_PER PIOB_PER
371 #define PWM_PIO_CODR PIOB_CODR
372 #define PWM_PIO_OER PIOB_OER
373 #define PWM_PIO_ABSR PIOB_ASR
375 #elif CPU_ARM_SAM7S_LARGE
376 #define PWM0 11 // PA11
377 #define PWM1 12 // PA12
378 #define PWM2 13 // PA13
379 #define PWM3 14 // PA14
381 #define PWM_PIO_PDR PIOA_PDR
382 #define PWM_PIO_PER PIOA_PER
383 #define PWM_PIO_CODR PIOA_CODR
384 #define PWM_PIO_OER PIOA_OER
385 #define PWM_PIO_ABSR PIOA_BSR
388 #error No PWM names of pins definition for selected ARM CPU
394 * TWI pins definition.
401 #elif CPU_ARM_SAM7S_LARGE
406 #error No TWI names of pins definition for selected ARM CPU
410 * ADC pins definition.
414 #define ADTRG 18 // PB18
415 #define AD0 23 // PB27
416 #define AD1 24 // PB28
417 #define AD2 25 // PB29
418 #define AD3 26 // PB30
420 #elif CPU_ARM_SAM7S_LARGE
421 #define ADTRG 18 // PA8
422 #define AD0 0 // PA17
423 #define AD1 1 // PA18
424 #define AD2 15 // PA19
425 #define AD3 16 // PA20
428 #error No ADC names of pins definition for selected ARM CPU
433 #endif /* AT91SAM7_H */