4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \author Francesco Sacchi <batt@develer.com>
35 * LPC23xx I/O registers.
41 #include <cfg/compiler.h>
43 #include <cpu/detect.h>
46 /* Embedded flash programming defines. */
47 #define IAP_ADDRESS 0x7ffffff1
49 typedef enum IapCommands
51 PREPARE_SECTOR_FOR_WRITE = 50,
52 COPY_RAM_TO_FLASH = 51,
54 BLANK_CHECK_SECTOR = 53,
62 #define FLASH_MEM_SIZE (504 * 1024L)
63 #define FLASH_PAGE_SIZE_BYTES 4096
64 #define FLASH_PAGE_4K_CNT 14
69 /* Vectored Interrupt Controller (VIC) */
70 #define VIC_BASE_ADDR 0xFFFFF000
71 #define VICIRQStatus (*(reg32_t *)(VIC_BASE_ADDR + 0x000))
72 #define VICFIQStatus (*(reg32_t *)(VIC_BASE_ADDR + 0x004))
73 #define VICRawIntr (*(reg32_t *)(VIC_BASE_ADDR + 0x008))
74 #define VICIntSelect (*(reg32_t *)(VIC_BASE_ADDR + 0x00C))
75 #define VICIntEnable (*(reg32_t *)(VIC_BASE_ADDR + 0x010))
76 #define VICIntEnClr (*(reg32_t *)(VIC_BASE_ADDR + 0x014))
77 #define VICSoftInt (*(reg32_t *)(VIC_BASE_ADDR + 0x018))
78 #define VICSoftIntClr (*(reg32_t *)(VIC_BASE_ADDR + 0x01C))
79 #define VICProtection (*(reg32_t *)(VIC_BASE_ADDR + 0x020))
80 #define VICSWPrioMask (*(reg32_t *)(VIC_BASE_ADDR + 0x024))
82 #define VICVectAddr0 (*(reg32_t *)(VIC_BASE_ADDR + 0x100))
83 #define VICVectAddr1 (*(reg32_t *)(VIC_BASE_ADDR + 0x104))
84 #define VICVectAddr2 (*(reg32_t *)(VIC_BASE_ADDR + 0x108))
85 #define VICVectAddr3 (*(reg32_t *)(VIC_BASE_ADDR + 0x10C))
86 #define VICVectAddr4 (*(reg32_t *)(VIC_BASE_ADDR + 0x110))
87 #define VICVectAddr5 (*(reg32_t *)(VIC_BASE_ADDR + 0x114))
88 #define VICVectAddr6 (*(reg32_t *)(VIC_BASE_ADDR + 0x118))
89 #define VICVectAddr7 (*(reg32_t *)(VIC_BASE_ADDR + 0x11C))
90 #define VICVectAddr8 (*(reg32_t *)(VIC_BASE_ADDR + 0x120))
91 #define VICVectAddr9 (*(reg32_t *)(VIC_BASE_ADDR + 0x124))
92 #define VICVectAddr10 (*(reg32_t *)(VIC_BASE_ADDR + 0x128))
93 #define VICVectAddr11 (*(reg32_t *)(VIC_BASE_ADDR + 0x12C))
94 #define VICVectAddr12 (*(reg32_t *)(VIC_BASE_ADDR + 0x130))
95 #define VICVectAddr13 (*(reg32_t *)(VIC_BASE_ADDR + 0x134))
96 #define VICVectAddr14 (*(reg32_t *)(VIC_BASE_ADDR + 0x138))
97 #define VICVectAddr15 (*(reg32_t *)(VIC_BASE_ADDR + 0x13C))
98 #define VICVectAddr16 (*(reg32_t *)(VIC_BASE_ADDR + 0x140))
99 #define VICVectAddr17 (*(reg32_t *)(VIC_BASE_ADDR + 0x144))
100 #define VICVectAddr18 (*(reg32_t *)(VIC_BASE_ADDR + 0x148))
101 #define VICVectAddr19 (*(reg32_t *)(VIC_BASE_ADDR + 0x14C))
102 #define VICVectAddr20 (*(reg32_t *)(VIC_BASE_ADDR + 0x150))
103 #define VICVectAddr21 (*(reg32_t *)(VIC_BASE_ADDR + 0x154))
104 #define VICVectAddr22 (*(reg32_t *)(VIC_BASE_ADDR + 0x158))
105 #define VICVectAddr23 (*(reg32_t *)(VIC_BASE_ADDR + 0x15C))
106 #define VICVectAddr24 (*(reg32_t *)(VIC_BASE_ADDR + 0x160))
107 #define VICVectAddr25 (*(reg32_t *)(VIC_BASE_ADDR + 0x164))
108 #define VICVectAddr26 (*(reg32_t *)(VIC_BASE_ADDR + 0x168))
109 #define VICVectAddr27 (*(reg32_t *)(VIC_BASE_ADDR + 0x16C))
110 #define VICVectAddr28 (*(reg32_t *)(VIC_BASE_ADDR + 0x170))
111 #define VICVectAddr29 (*(reg32_t *)(VIC_BASE_ADDR + 0x174))
112 #define VICVectAddr30 (*(reg32_t *)(VIC_BASE_ADDR + 0x178))
113 #define VICVectAddr31 (*(reg32_t *)(VIC_BASE_ADDR + 0x17C))
115 /* The name convention below is from previous LPC2000 family MCUs, in LPC23xx/24xx,
116 these registers are known as "VICVectPriority(x)". */
117 #define VICVectCntl0 (*(reg32_t *)(VIC_BASE_ADDR + 0x200))
118 #define VICVectCntl1 (*(reg32_t *)(VIC_BASE_ADDR + 0x204))
119 #define VICVectCntl2 (*(reg32_t *)(VIC_BASE_ADDR + 0x208))
120 #define VICVectCntl3 (*(reg32_t *)(VIC_BASE_ADDR + 0x20C))
121 #define VICVectCntl4 (*(reg32_t *)(VIC_BASE_ADDR + 0x210))
122 #define VICVectCntl5 (*(reg32_t *)(VIC_BASE_ADDR + 0x214))
123 #define VICVectCntl6 (*(reg32_t *)(VIC_BASE_ADDR + 0x218))
124 #define VICVectCntl7 (*(reg32_t *)(VIC_BASE_ADDR + 0x21C))
125 #define VICVectCntl8 (*(reg32_t *)(VIC_BASE_ADDR + 0x220))
126 #define VICVectCntl9 (*(reg32_t *)(VIC_BASE_ADDR + 0x224))
127 #define VICVectCntl10 (*(reg32_t *)(VIC_BASE_ADDR + 0x228))
128 #define VICVectCntl11 (*(reg32_t *)(VIC_BASE_ADDR + 0x22C))
129 #define VICVectCntl12 (*(reg32_t *)(VIC_BASE_ADDR + 0x230))
130 #define VICVectCntl13 (*(reg32_t *)(VIC_BASE_ADDR + 0x234))
131 #define VICVectCntl14 (*(reg32_t *)(VIC_BASE_ADDR + 0x238))
132 #define VICVectCntl15 (*(reg32_t *)(VIC_BASE_ADDR + 0x23C))
133 #define VICVectCntl16 (*(reg32_t *)(VIC_BASE_ADDR + 0x240))
134 #define VICVectCntl17 (*(reg32_t *)(VIC_BASE_ADDR + 0x244))
135 #define VICVectCntl18 (*(reg32_t *)(VIC_BASE_ADDR + 0x248))
136 #define VICVectCntl19 (*(reg32_t *)(VIC_BASE_ADDR + 0x24C))
137 #define VICVectCntl20 (*(reg32_t *)(VIC_BASE_ADDR + 0x250))
138 #define VICVectCntl21 (*(reg32_t *)(VIC_BASE_ADDR + 0x254))
139 #define VICVectCntl22 (*(reg32_t *)(VIC_BASE_ADDR + 0x258))
140 #define VICVectCntl23 (*(reg32_t *)(VIC_BASE_ADDR + 0x25C))
141 #define VICVectCntl24 (*(reg32_t *)(VIC_BASE_ADDR + 0x260))
142 #define VICVectCntl25 (*(reg32_t *)(VIC_BASE_ADDR + 0x264))
143 #define VICVectCntl26 (*(reg32_t *)(VIC_BASE_ADDR + 0x268))
144 #define VICVectCntl27 (*(reg32_t *)(VIC_BASE_ADDR + 0x26C))
145 #define VICVectCntl28 (*(reg32_t *)(VIC_BASE_ADDR + 0x270))
146 #define VICVectCntl29 (*(reg32_t *)(VIC_BASE_ADDR + 0x274))
147 #define VICVectCntl30 (*(reg32_t *)(VIC_BASE_ADDR + 0x278))
148 #define VICVectCntl31 (*(reg32_t *)(VIC_BASE_ADDR + 0x27C))
150 #define VICVectAddr (*(reg32_t *)(VIC_BASE_ADDR + 0xF00))
153 /* Pin Connect Block */
154 #define PINSEL_BASE_ADDR 0xE002C000
155 #define PINSEL0 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x00))
156 #define PINSEL1 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x04))
157 #define PINSEL2 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x08))
158 #define PINSEL3 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x0C))
159 #define PINSEL4 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x10))
160 #define PINSEL5 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x14))
161 #define PINSEL6 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x18))
162 #define PINSEL7 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x1C))
163 #define PINSEL8 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x20))
164 #define PINSEL9 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x24))
165 #define PINSEL10 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x28))
167 #define PINSEL0_OFF 0x00
168 #define PINSEL1_OFF 0x04
169 #define PINSEL2_OFF 0x08
170 #define PINSEL3_OFF 0x0C
171 #define PINSEL4_OFF 0x10
172 #define PINSEL5_OFF 0x14
173 #define PINSEL6_OFF 0x18
174 #define PINSEL7_OFF 0x1C
175 #define PINSEL8_OFF 0x20
176 #define PINSEL9_OFF 0x24
177 #define PINSEL10_OFF 0x28
179 #define PINMODE0 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x40))
180 #define PINMODE1 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x44))
181 #define PINMODE2 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x48))
182 #define PINMODE3 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x4C))
183 #define PINMODE4 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x50))
184 #define PINMODE5 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x54))
185 #define PINMODE6 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x58))
186 #define PINMODE7 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x5C))
187 #define PINMODE8 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x60))
188 #define PINMODE9 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x64))
190 /* General Purpose Input/Output (GPIO) */
191 #define GPIO_BASE_ADDR 0xE0028000
192 #define IOPIN0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x00))
193 #define IOSET0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x04))
194 #define IODIR0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x08))
195 #define IOCLR0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x0C))
196 #define IOPIN1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x10))
197 #define IOSET1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x14))
198 #define IODIR1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x18))
199 #define IOCLR1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x1C))
201 /* GPIO Interrupt Registers */
202 #define IO0_INT_EN_R (*(reg32_t *)(GPIO_BASE_ADDR + 0x90))
203 #define IO0_INT_EN_F (*(reg32_t *)(GPIO_BASE_ADDR + 0x94))
204 #define IO0_INT_STAT_R (*(reg32_t *)(GPIO_BASE_ADDR + 0x84))
205 #define IO0_INT_STAT_F (*(reg32_t *)(GPIO_BASE_ADDR + 0x88))
206 #define IO0_INT_CLR (*(reg32_t *)(GPIO_BASE_ADDR + 0x8C))
208 #define IO2_INT_EN_R (*(reg32_t *)(GPIO_BASE_ADDR + 0xB0))
209 #define IO2_INT_EN_F (*(reg32_t *)(GPIO_BASE_ADDR + 0xB4))
210 #define IO2_INT_STAT_R (*(reg32_t *)(GPIO_BASE_ADDR + 0xA4))
211 #define IO2_INT_STAT_F (*(reg32_t *)(GPIO_BASE_ADDR + 0xA8))
212 #define IO2_INT_CLR (*(reg32_t *)(GPIO_BASE_ADDR + 0xAC))
214 #define IO_INT_STAT (*(reg32_t *)(GPIO_BASE_ADDR + 0x80))
216 #define PARTCFG_BASE_ADDR 0x3FFF8000
217 #define PARTCFG (*(reg32_t *)(PARTCFG_BASE_ADDR + 0x00))
220 #define FIO_BASE_ADDR 0x3FFFC000
221 #define FIO0DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x00))
222 #define FIO0MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x10))
223 #define FIO0PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x14))
224 #define FIO0SET (*(reg32_t *)(FIO_BASE_ADDR + 0x18))
225 #define FIO0CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x1C))
227 #define FIO1DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x20))
228 #define FIO1MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x30))
229 #define FIO1PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x34))
230 #define FIO1SET (*(reg32_t *)(FIO_BASE_ADDR + 0x38))
231 #define FIO1CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x3C))
233 #define FIO2DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x40))
234 #define FIO2MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x50))
235 #define FIO2PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x54))
236 #define FIO2SET (*(reg32_t *)(FIO_BASE_ADDR + 0x58))
237 #define FIO2CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x5C))
239 #define FIO3DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x60))
240 #define FIO3MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x70))
241 #define FIO3PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x74))
242 #define FIO3SET (*(reg32_t *)(FIO_BASE_ADDR + 0x78))
243 #define FIO3CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x7C))
245 #define FIO4DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x80))
246 #define FIO4MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x90))
247 #define FIO4PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x94))
248 #define FIO4SET (*(reg32_t *)(FIO_BASE_ADDR + 0x98))
249 #define FIO4CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x9C))
251 /* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
252 #define FIO0DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x00))
253 #define FIO1DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x20))
254 #define FIO2DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x40))
255 #define FIO3DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x60))
256 #define FIO4DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x80))
258 #define FIO0DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x01))
259 #define FIO1DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x21))
260 #define FIO2DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x41))
261 #define FIO3DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x61))
262 #define FIO4DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x81))
264 #define FIO0DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x02))
265 #define FIO1DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x22))
266 #define FIO2DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x42))
267 #define FIO3DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x62))
268 #define FIO4DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x82))
270 #define FIO0DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x03))
271 #define FIO1DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x23))
272 #define FIO2DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x43))
273 #define FIO3DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x63))
274 #define FIO4DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x83))
276 #define FIO0DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x00))
277 #define FIO1DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x20))
278 #define FIO2DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x40))
279 #define FIO3DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x60))
280 #define FIO4DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x80))
282 #define FIO0DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x02))
283 #define FIO1DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x22))
284 #define FIO2DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x42))
285 #define FIO3DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x62))
286 #define FIO4DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x82))
288 #define FIO0MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x10))
289 #define FIO1MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x30))
290 #define FIO2MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x50))
291 #define FIO3MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x70))
292 #define FIO4MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x90))
294 #define FIO0MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x11))
295 #define FIO1MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x21))
296 #define FIO2MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x51))
297 #define FIO3MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x71))
298 #define FIO4MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x91))
300 #define FIO0MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x12))
301 #define FIO1MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x32))
302 #define FIO2MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x52))
303 #define FIO3MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x72))
304 #define FIO4MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x92))
306 #define FIO0MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x13))
307 #define FIO1MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x33))
308 #define FIO2MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x53))
309 #define FIO3MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x73))
310 #define FIO4MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x93))
312 #define FIO0MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x10))
313 #define FIO1MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x30))
314 #define FIO2MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x50))
315 #define FIO3MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x70))
316 #define FIO4MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x90))
318 #define FIO0MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x12))
319 #define FIO1MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x32))
320 #define FIO2MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x52))
321 #define FIO3MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x72))
322 #define FIO4MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x92))
324 #define FIO0PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x14))
325 #define FIO1PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x34))
326 #define FIO2PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x54))
327 #define FIO3PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x74))
328 #define FIO4PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x94))
330 #define FIO0PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x15))
331 #define FIO1PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x25))
332 #define FIO2PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x55))
333 #define FIO3PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x75))
334 #define FIO4PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x95))
336 #define FIO0PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x16))
337 #define FIO1PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x36))
338 #define FIO2PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x56))
339 #define FIO3PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x76))
340 #define FIO4PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x96))
342 #define FIO0PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x17))
343 #define FIO1PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x37))
344 #define FIO2PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x57))
345 #define FIO3PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x77))
346 #define FIO4PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x97))
348 #define FIO0PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x14))
349 #define FIO1PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x34))
350 #define FIO2PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x54))
351 #define FIO3PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x74))
352 #define FIO4PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x94))
354 #define FIO0PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x16))
355 #define FIO1PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x36))
356 #define FIO2PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x56))
357 #define FIO3PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x76))
358 #define FIO4PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x96))
360 #define FIO0SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x18))
361 #define FIO1SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x38))
362 #define FIO2SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x58))
363 #define FIO3SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x78))
364 #define FIO4SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x98))
366 #define FIO0SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x19))
367 #define FIO1SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x29))
368 #define FIO2SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x59))
369 #define FIO3SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x79))
370 #define FIO4SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x99))
372 #define FIO0SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x1A))
373 #define FIO1SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x3A))
374 #define FIO2SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x5A))
375 #define FIO3SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x7A))
376 #define FIO4SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x9A))
378 #define FIO0SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x1B))
379 #define FIO1SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x3B))
380 #define FIO2SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x5B))
381 #define FIO3SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x7B))
382 #define FIO4SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x9B))
384 #define FIO0SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x18))
385 #define FIO1SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x38))
386 #define FIO2SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x58))
387 #define FIO3SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x78))
388 #define FIO4SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x98))
390 #define FIO0SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x1A))
391 #define FIO1SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x3A))
392 #define FIO2SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x5A))
393 #define FIO3SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x7A))
394 #define FIO4SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x9A))
396 #define FIO0CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x1C))
397 #define FIO1CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x3C))
398 #define FIO2CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x5C))
399 #define FIO3CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x7C))
400 #define FIO4CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x9C))
402 #define FIO0CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x1D))
403 #define FIO1CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x2D))
404 #define FIO2CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x5D))
405 #define FIO3CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x7D))
406 #define FIO4CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x9D))
408 #define FIO0CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x1E))
409 #define FIO1CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x3E))
410 #define FIO2CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x5E))
411 #define FIO3CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x7E))
412 #define FIO4CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x9E))
414 #define FIO0CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x1F))
415 #define FIO1CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x3F))
416 #define FIO2CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x5F))
417 #define FIO3CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x7F))
418 #define FIO4CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x9F))
420 #define FIO0CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x1C))
421 #define FIO1CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x3C))
422 #define FIO2CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x5C))
423 #define FIO3CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x7C))
424 #define FIO4CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x9C))
426 #define FIO0CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x1E))
427 #define FIO1CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x3E))
428 #define FIO2CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x5E))
429 #define FIO3CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x7E))
430 #define FIO4CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x9E))
433 /* System Control Block(SCB) modules include Memory Accelerator Module,
434 Phase Locked Loop, VPB divider, Power Control, External Interrupt,
435 Reset, and Code Security/Debugging */
436 #define SCB_BASE_ADDR 0xE01FC000
438 /* Memory Accelerator Module (MAM) */
439 #define MAMCR (*(reg32_t *)(SCB_BASE_ADDR + 0x000))
440 #define MAMTIM (*(reg32_t *)(SCB_BASE_ADDR + 0x004))
441 #define MEMMAP (*(reg32_t *)(SCB_BASE_ADDR + 0x040))
443 /* Phase Locked Loop (PLL) */
444 #define PLLCON (*(reg32_t *)(SCB_BASE_ADDR + 0x080))
445 #define PLLCFG (*(reg32_t *)(SCB_BASE_ADDR + 0x084))
446 #define PLLSTAT (*(reg32_t *)(SCB_BASE_ADDR + 0x088))
447 #define PLLFEED (*(reg32_t *)(SCB_BASE_ADDR + 0x08C))
450 #define PCON (*(reg32_t *)(SCB_BASE_ADDR + 0x0C0))
451 #define PCONP (*(reg32_t *)(SCB_BASE_ADDR + 0x0C4))
452 #define PCONP_PCI2C0 7
453 #define PCONP_PCI2C1 19
454 #define PCONP_PCI2C2 26
458 // #define APBDIV (*(reg32_t *)(SCB_BASE_ADDR + 0x100))
459 #define CCLKCFG (*(reg32_t *)(SCB_BASE_ADDR + 0x104))
460 #define USBCLKCFG (*(reg32_t *)(SCB_BASE_ADDR + 0x108))
461 #define CLKSRCSEL (*(reg32_t *)(SCB_BASE_ADDR + 0x10C))
462 #define PCLKSEL0 (*(reg32_t *)(SCB_BASE_ADDR + 0x1A8))
463 #define PCLKSEL1 (*(reg32_t *)(SCB_BASE_ADDR + 0x1AC))
465 #define CCLKCFG_OFF 0x104
466 #define USBCLKCFG_OFF 0x108
467 #define CLKSRCSEL_OFF 0x10C
468 #define PCLKSEL0_OFF 0x1A8
469 #define PCLKSEL1_OFF 0x1AC
472 /* External Interrupts */
473 #define EXTINT (*(reg32_t *)(SCB_BASE_ADDR + 0x140))
474 #define INTWAKE (*(reg32_t *)(SCB_BASE_ADDR + 0x144))
475 #define EXTMODE (*(reg32_t *)(SCB_BASE_ADDR + 0x148))
476 #define EXTPOLAR (*(reg32_t *)(SCB_BASE_ADDR + 0x14C))
478 /* Reset, reset source identification */
479 #define RSIR (*(reg32_t *)(SCB_BASE_ADDR + 0x180))
481 /* RSID, code security protection */
482 #define CSPR (*(reg32_t *)(SCB_BASE_ADDR + 0x184))
484 /* AHB configuration */
485 #define AHBCFG1 (*(reg32_t *)(SCB_BASE_ADDR + 0x188))
486 #define AHBCFG2 (*(reg32_t *)(SCB_BASE_ADDR + 0x18C))
488 /* System Controls and Status */
489 #define SCS (*(reg32_t *)(SCB_BASE_ADDR + 0x1A0))
491 /* MPMC(EMC) registers, note: all the external memory controller(EMC) registers
492 are for LPC24xx only. */
493 #define STATIC_MEM0_BASE 0x80000000
494 #define STATIC_MEM1_BASE 0x81000000
495 #define STATIC_MEM2_BASE 0x82000000
496 #define STATIC_MEM3_BASE 0x83000000
498 #define DYNAMIC_MEM0_BASE 0xA0000000
499 #define DYNAMIC_MEM1_BASE 0xB0000000
500 #define DYNAMIC_MEM2_BASE 0xC0000000
501 #define DYNAMIC_MEM3_BASE 0xD0000000
503 /* External Memory Controller (EMC) */
504 #define EMC_BASE_ADDR 0xFFE08000
505 #define EMC_CTRL (*(reg32_t *)(EMC_BASE_ADDR + 0x000))
506 #define EMC_STAT (*(reg32_t *)(EMC_BASE_ADDR + 0x004))
507 #define EMC_CONFIG (*(reg32_t *)(EMC_BASE_ADDR + 0x008))
509 /* Dynamic RAM access registers */
510 #define EMC_DYN_CTRL (*(reg32_t *)(EMC_BASE_ADDR + 0x020))
511 #define EMC_DYN_RFSH (*(reg32_t *)(EMC_BASE_ADDR + 0x024))
512 #define EMC_DYN_RD_CFG (*(reg32_t *)(EMC_BASE_ADDR + 0x028))
513 #define EMC_DYN_RP (*(reg32_t *)(EMC_BASE_ADDR + 0x030))
514 #define EMC_DYN_RAS (*(reg32_t *)(EMC_BASE_ADDR + 0x034))
515 #define EMC_DYN_SREX (*(reg32_t *)(EMC_BASE_ADDR + 0x038))
516 #define EMC_DYN_APR (*(reg32_t *)(EMC_BASE_ADDR + 0x03C))
517 #define EMC_DYN_DAL (*(reg32_t *)(EMC_BASE_ADDR + 0x040))
518 #define EMC_DYN_WR (*(reg32_t *)(EMC_BASE_ADDR + 0x044))
519 #define EMC_DYN_RC (*(reg32_t *)(EMC_BASE_ADDR + 0x048))
520 #define EMC_DYN_RFC (*(reg32_t *)(EMC_BASE_ADDR + 0x04C))
521 #define EMC_DYN_XSR (*(reg32_t *)(EMC_BASE_ADDR + 0x050))
522 #define EMC_DYN_RRD (*(reg32_t *)(EMC_BASE_ADDR + 0x054))
523 #define EMC_DYN_MRD (*(reg32_t *)(EMC_BASE_ADDR + 0x058))
525 #define EMC_DYN_CFG0 (*(reg32_t *)(EMC_BASE_ADDR + 0x100))
526 #define EMC_DYN_RASCAS0 (*(reg32_t *)(EMC_BASE_ADDR + 0x104))
527 #define EMC_DYN_CFG1 (*(reg32_t *)(EMC_BASE_ADDR + 0x140))
528 #define EMC_DYN_RASCAS1 (*(reg32_t *)(EMC_BASE_ADDR + 0x144))
529 #define EMC_DYN_CFG2 (*(reg32_t *)(EMC_BASE_ADDR + 0x160))
530 #define EMC_DYN_RASCAS2 (*(reg32_t *)(EMC_BASE_ADDR + 0x164))
531 #define EMC_DYN_CFG3 (*(reg32_t *)(EMC_BASE_ADDR + 0x180))
532 #define EMC_DYN_RASCAS3 (*(reg32_t *)(EMC_BASE_ADDR + 0x184))
534 /* static RAM access registers */
535 #define EMC_STA_CFG0 (*(reg32_t *)(EMC_BASE_ADDR + 0x200))
536 #define EMC_STA_WAITWEN0 (*(reg32_t *)(EMC_BASE_ADDR + 0x204))
537 #define EMC_STA_WAITOEN0 (*(reg32_t *)(EMC_BASE_ADDR + 0x208))
538 #define EMC_STA_WAITRD0 (*(reg32_t *)(EMC_BASE_ADDR + 0x20C))
539 #define EMC_STA_WAITPAGE0 (*(reg32_t *)(EMC_BASE_ADDR + 0x210))
540 #define EMC_STA_WAITWR0 (*(reg32_t *)(EMC_BASE_ADDR + 0x214))
541 #define EMC_STA_WAITTURN0 (*(reg32_t *)(EMC_BASE_ADDR + 0x218))
543 #define EMC_STA_CFG1 (*(reg32_t *)(EMC_BASE_ADDR + 0x220))
544 #define EMC_STA_WAITWEN1 (*(reg32_t *)(EMC_BASE_ADDR + 0x224))
545 #define EMC_STA_WAITOEN1 (*(reg32_t *)(EMC_BASE_ADDR + 0x228))
546 #define EMC_STA_WAITRD1 (*(reg32_t *)(EMC_BASE_ADDR + 0x22C))
547 #define EMC_STA_WAITPAGE1 (*(reg32_t *)(EMC_BASE_ADDR + 0x230))
548 #define EMC_STA_WAITWR1 (*(reg32_t *)(EMC_BASE_ADDR + 0x234))
549 #define EMC_STA_WAITTURN1 (*(reg32_t *)(EMC_BASE_ADDR + 0x238))
551 #define EMC_STA_CFG2 (*(reg32_t *)(EMC_BASE_ADDR + 0x240))
552 #define EMC_STA_WAITWEN2 (*(reg32_t *)(EMC_BASE_ADDR + 0x244))
553 #define EMC_STA_WAITOEN2 (*(reg32_t *)(EMC_BASE_ADDR + 0x248))
554 #define EMC_STA_WAITRD2 (*(reg32_t *)(EMC_BASE_ADDR + 0x24C))
555 #define EMC_STA_WAITPAGE2 (*(reg32_t *)(EMC_BASE_ADDR + 0x250))
556 #define EMC_STA_WAITWR2 (*(reg32_t *)(EMC_BASE_ADDR + 0x254))
557 #define EMC_STA_WAITTURN2 (*(reg32_t *)(EMC_BASE_ADDR + 0x258))
559 #define EMC_STA_CFG3 (*(reg32_t *)(EMC_BASE_ADDR + 0x260))
560 #define EMC_STA_WAITWEN3 (*(reg32_t *)(EMC_BASE_ADDR + 0x264))
561 #define EMC_STA_WAITOEN3 (*(reg32_t *)(EMC_BASE_ADDR + 0x268))
562 #define EMC_STA_WAITRD3 (*(reg32_t *)(EMC_BASE_ADDR + 0x26C))
563 #define EMC_STA_WAITPAGE3 (*(reg32_t *)(EMC_BASE_ADDR + 0x270))
564 #define EMC_STA_WAITWR3 (*(reg32_t *)(EMC_BASE_ADDR + 0x274))
565 #define EMC_STA_WAITTURN3 (*(reg32_t *)(EMC_BASE_ADDR + 0x278))
567 #define EMC_STA_EXT_WAIT (*(reg32_t *)(EMC_BASE_ADDR + 0x880))
571 #define TMR0_BASE_ADDR 0xE0004000
572 #define T0IR (*(reg32_t *)(TMR0_BASE_ADDR + 0x00))
573 #define T0TCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x04))
574 #define T0TC (*(reg32_t *)(TMR0_BASE_ADDR + 0x08))
575 #define T0PR (*(reg32_t *)(TMR0_BASE_ADDR + 0x0C))
576 #define T0PC (*(reg32_t *)(TMR0_BASE_ADDR + 0x10))
577 #define T0MCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x14))
578 #define T0MR0 (*(reg32_t *)(TMR0_BASE_ADDR + 0x18))
579 #define T0MR1 (*(reg32_t *)(TMR0_BASE_ADDR + 0x1C))
580 #define T0MR2 (*(reg32_t *)(TMR0_BASE_ADDR + 0x20))
581 #define T0MR3 (*(reg32_t *)(TMR0_BASE_ADDR + 0x24))
582 #define T0CCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x28))
583 #define T0CR0 (*(reg32_t *)(TMR0_BASE_ADDR + 0x2C))
584 #define T0CR1 (*(reg32_t *)(TMR0_BASE_ADDR + 0x30))
585 #define T0CR2 (*(reg32_t *)(TMR0_BASE_ADDR + 0x34))
586 #define T0CR3 (*(reg32_t *)(TMR0_BASE_ADDR + 0x38))
587 #define T0EMR (*(reg32_t *)(TMR0_BASE_ADDR + 0x3C))
588 #define T0CTCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x70))
591 #define TMR1_BASE_ADDR 0xE0008000
592 #define T1IR (*(reg32_t *)(TMR1_BASE_ADDR + 0x00))
593 #define T1TCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x04))
594 #define T1TC (*(reg32_t *)(TMR1_BASE_ADDR + 0x08))
595 #define T1PR (*(reg32_t *)(TMR1_BASE_ADDR + 0x0C))
596 #define T1PC (*(reg32_t *)(TMR1_BASE_ADDR + 0x10))
597 #define T1MCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x14))
598 #define T1MR0 (*(reg32_t *)(TMR1_BASE_ADDR + 0x18))
599 #define T1MR1 (*(reg32_t *)(TMR1_BASE_ADDR + 0x1C))
600 #define T1MR2 (*(reg32_t *)(TMR1_BASE_ADDR + 0x20))
601 #define T1MR3 (*(reg32_t *)(TMR1_BASE_ADDR + 0x24))
602 #define T1CCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x28))
603 #define T1CR0 (*(reg32_t *)(TMR1_BASE_ADDR + 0x2C))
604 #define T1CR1 (*(reg32_t *)(TMR1_BASE_ADDR + 0x30))
605 #define T1CR2 (*(reg32_t *)(TMR1_BASE_ADDR + 0x34))
606 #define T1CR3 (*(reg32_t *)(TMR1_BASE_ADDR + 0x38))
607 #define T1EMR (*(reg32_t *)(TMR1_BASE_ADDR + 0x3C))
608 #define T1CTCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x70))
611 #define TMR2_BASE_ADDR 0xE0070000
612 #define T2IR (*(reg32_t *)(TMR2_BASE_ADDR + 0x00))
613 #define T2TCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x04))
614 #define T2TC (*(reg32_t *)(TMR2_BASE_ADDR + 0x08))
615 #define T2PR (*(reg32_t *)(TMR2_BASE_ADDR + 0x0C))
616 #define T2PC (*(reg32_t *)(TMR2_BASE_ADDR + 0x10))
617 #define T2MCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x14))
618 #define T2MR0 (*(reg32_t *)(TMR2_BASE_ADDR + 0x18))
619 #define T2MR1 (*(reg32_t *)(TMR2_BASE_ADDR + 0x1C))
620 #define T2MR2 (*(reg32_t *)(TMR2_BASE_ADDR + 0x20))
621 #define T2MR3 (*(reg32_t *)(TMR2_BASE_ADDR + 0x24))
622 #define T2CCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x28))
623 #define T2CR0 (*(reg32_t *)(TMR2_BASE_ADDR + 0x2C))
624 #define T2CR1 (*(reg32_t *)(TMR2_BASE_ADDR + 0x30))
625 #define T2CR2 (*(reg32_t *)(TMR2_BASE_ADDR + 0x34))
626 #define T2CR3 (*(reg32_t *)(TMR2_BASE_ADDR + 0x38))
627 #define T2EMR (*(reg32_t *)(TMR2_BASE_ADDR + 0x3C))
628 #define T2CTCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x70))
631 #define TMR3_BASE_ADDR 0xE0074000
632 #define T3IR (*(reg32_t *)(TMR3_BASE_ADDR + 0x00))
633 #define T3TCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x04))
634 #define T3TC (*(reg32_t *)(TMR3_BASE_ADDR + 0x08))
635 #define T3PR (*(reg32_t *)(TMR3_BASE_ADDR + 0x0C))
636 #define T3PC (*(reg32_t *)(TMR3_BASE_ADDR + 0x10))
637 #define T3MCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x14))
638 #define T3MR0 (*(reg32_t *)(TMR3_BASE_ADDR + 0x18))
639 #define T3MR1 (*(reg32_t *)(TMR3_BASE_ADDR + 0x1C))
640 #define T3MR2 (*(reg32_t *)(TMR3_BASE_ADDR + 0x20))
641 #define T3MR3 (*(reg32_t *)(TMR3_BASE_ADDR + 0x24))
642 #define T3CCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x28))
643 #define T3CR0 (*(reg32_t *)(TMR3_BASE_ADDR + 0x2C))
644 #define T3CR1 (*(reg32_t *)(TMR3_BASE_ADDR + 0x30))
645 #define T3CR2 (*(reg32_t *)(TMR3_BASE_ADDR + 0x34))
646 #define T3CR3 (*(reg32_t *)(TMR3_BASE_ADDR + 0x38))
647 #define T3EMR (*(reg32_t *)(TMR3_BASE_ADDR + 0x3C))
648 #define T3CTCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x70))
651 /* Pulse Width Modulator (PWM) */
652 #define PWM0_BASE_ADDR 0xE0014000
653 #define PWM0IR (*(reg32_t *)(PWM0_BASE_ADDR + 0x00))
654 #define PWM0TCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x04))
655 #define PWM0TC (*(reg32_t *)(PWM0_BASE_ADDR + 0x08))
656 #define PWM0PR (*(reg32_t *)(PWM0_BASE_ADDR + 0x0C))
657 #define PWM0PC (*(reg32_t *)(PWM0_BASE_ADDR + 0x10))
658 #define PWM0MCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x14))
659 #define PWM0MR0 (*(reg32_t *)(PWM0_BASE_ADDR + 0x18))
660 #define PWM0MR1 (*(reg32_t *)(PWM0_BASE_ADDR + 0x1C))
661 #define PWM0MR2 (*(reg32_t *)(PWM0_BASE_ADDR + 0x20))
662 #define PWM0MR3 (*(reg32_t *)(PWM0_BASE_ADDR + 0x24))
663 #define PWM0CCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x28))
664 #define PWM0CR0 (*(reg32_t *)(PWM0_BASE_ADDR + 0x2C))
665 #define PWM0CR1 (*(reg32_t *)(PWM0_BASE_ADDR + 0x30))
666 #define PWM0CR2 (*(reg32_t *)(PWM0_BASE_ADDR + 0x34))
667 #define PWM0CR3 (*(reg32_t *)(PWM0_BASE_ADDR + 0x38))
668 #define PWM0EMR (*(reg32_t *)(PWM0_BASE_ADDR + 0x3C))
669 #define PWM0MR4 (*(reg32_t *)(PWM0_BASE_ADDR + 0x40))
670 #define PWM0MR5 (*(reg32_t *)(PWM0_BASE_ADDR + 0x44))
671 #define PWM0MR6 (*(reg32_t *)(PWM0_BASE_ADDR + 0x48))
672 #define PWM0PCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x4C))
673 #define PWM0LER (*(reg32_t *)(PWM0_BASE_ADDR + 0x50))
674 #define PWM0CTCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x70))
676 #define PWM1_BASE_ADDR 0xE0018000
677 #define PWM1IR (*(reg32_t *)(PWM1_BASE_ADDR + 0x00))
678 #define PWM1TCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x04))
679 #define PWM1TC (*(reg32_t *)(PWM1_BASE_ADDR + 0x08))
680 #define PWM1PR (*(reg32_t *)(PWM1_BASE_ADDR + 0x0C))
681 #define PWM1PC (*(reg32_t *)(PWM1_BASE_ADDR + 0x10))
682 #define PWM1MCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x14))
683 #define PWM1MR0 (*(reg32_t *)(PWM1_BASE_ADDR + 0x18))
684 #define PWM1MR1 (*(reg32_t *)(PWM1_BASE_ADDR + 0x1C))
685 #define PWM1MR2 (*(reg32_t *)(PWM1_BASE_ADDR + 0x20))
686 #define PWM1MR3 (*(reg32_t *)(PWM1_BASE_ADDR + 0x24))
687 #define PWM1CCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x28))
688 #define PWM1CR0 (*(reg32_t *)(PWM1_BASE_ADDR + 0x2C))
689 #define PWM1CR1 (*(reg32_t *)(PWM1_BASE_ADDR + 0x30))
690 #define PWM1CR2 (*(reg32_t *)(PWM1_BASE_ADDR + 0x34))
691 #define PWM1CR3 (*(reg32_t *)(PWM1_BASE_ADDR + 0x38))
692 #define PWM1EMR (*(reg32_t *)(PWM1_BASE_ADDR + 0x3C))
693 #define PWM1MR4 (*(reg32_t *)(PWM1_BASE_ADDR + 0x40))
694 #define PWM1MR5 (*(reg32_t *)(PWM1_BASE_ADDR + 0x44))
695 #define PWM1MR6 (*(reg32_t *)(PWM1_BASE_ADDR + 0x48))
696 #define PWM1PCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x4C))
697 #define PWM1LER (*(reg32_t *)(PWM1_BASE_ADDR + 0x50))
698 #define PWM1CTCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x70))
701 /* Universal Asynchronous Receiver Transmitter 0 (UART0) */
702 #define UART0_BASE_ADDR 0xE000C000
703 #define U0RBR (*(reg32_t *)(UART0_BASE_ADDR + 0x00))
704 #define U0THR (*(reg32_t *)(UART0_BASE_ADDR + 0x00))
705 #define U0DLL (*(reg32_t *)(UART0_BASE_ADDR + 0x00))
706 #define U0DLM (*(reg32_t *)(UART0_BASE_ADDR + 0x04))
707 #define U0IER (*(reg32_t *)(UART0_BASE_ADDR + 0x04))
708 #define U0IIR (*(reg32_t *)(UART0_BASE_ADDR + 0x08))
709 #define U0FCR (*(reg32_t *)(UART0_BASE_ADDR + 0x08))
710 #define U0LCR (*(reg32_t *)(UART0_BASE_ADDR + 0x0C))
711 #define U0LSR (*(reg32_t *)(UART0_BASE_ADDR + 0x14))
712 #define U0SCR (*(reg32_t *)(UART0_BASE_ADDR + 0x1C))
713 #define U0ACR (*(reg32_t *)(UART0_BASE_ADDR + 0x20))
714 #define U0ICR (*(reg32_t *)(UART0_BASE_ADDR + 0x24))
715 #define U0FDR (*(reg32_t *)(UART0_BASE_ADDR + 0x28))
716 #define U0TER (*(reg32_t *)(UART0_BASE_ADDR + 0x30))
718 /* Universal Asynchronous Receiver Transmitter 1 (UART1) */
719 #define UART1_BASE_ADDR 0xE0010000
720 #define U1RBR (*(reg32_t *)(UART1_BASE_ADDR + 0x00))
721 #define U1THR (*(reg32_t *)(UART1_BASE_ADDR + 0x00))
722 #define U1DLL (*(reg32_t *)(UART1_BASE_ADDR + 0x00))
723 #define U1DLM (*(reg32_t *)(UART1_BASE_ADDR + 0x04))
724 #define U1IER (*(reg32_t *)(UART1_BASE_ADDR + 0x04))
725 #define U1IIR (*(reg32_t *)(UART1_BASE_ADDR + 0x08))
726 #define U1FCR (*(reg32_t *)(UART1_BASE_ADDR + 0x08))
727 #define U1LCR (*(reg32_t *)(UART1_BASE_ADDR + 0x0C))
728 #define U1MCR (*(reg32_t *)(UART1_BASE_ADDR + 0x10))
729 #define U1LSR (*(reg32_t *)(UART1_BASE_ADDR + 0x14))
730 #define U1MSR (*(reg32_t *)(UART1_BASE_ADDR + 0x18))
731 #define U1SCR (*(reg32_t *)(UART1_BASE_ADDR + 0x1C))
732 #define U1ACR (*(reg32_t *)(UART1_BASE_ADDR + 0x20))
733 #define U1FDR (*(reg32_t *)(UART1_BASE_ADDR + 0x28))
734 #define U1TER (*(reg32_t *)(UART1_BASE_ADDR + 0x30))
736 /* Universal Asynchronous Receiver Transmitter 2 (UART2) */
737 #define UART2_BASE_ADDR 0xE0078000
738 #define U2RBR (*(reg32_t *)(UART2_BASE_ADDR + 0x00))
739 #define U2THR (*(reg32_t *)(UART2_BASE_ADDR + 0x00))
740 #define U2DLL (*(reg32_t *)(UART2_BASE_ADDR + 0x00))
741 #define U2DLM (*(reg32_t *)(UART2_BASE_ADDR + 0x04))
742 #define U2IER (*(reg32_t *)(UART2_BASE_ADDR + 0x04))
743 #define U2IIR (*(reg32_t *)(UART2_BASE_ADDR + 0x08))
744 #define U2FCR (*(reg32_t *)(UART2_BASE_ADDR + 0x08))
745 #define U2LCR (*(reg32_t *)(UART2_BASE_ADDR + 0x0C))
746 #define U2LSR (*(reg32_t *)(UART2_BASE_ADDR + 0x14))
747 #define U2SCR (*(reg32_t *)(UART2_BASE_ADDR + 0x1C))
748 #define U2ACR (*(reg32_t *)(UART2_BASE_ADDR + 0x20))
749 #define U2ICR (*(reg32_t *)(UART2_BASE_ADDR + 0x24))
750 #define U2FDR (*(reg32_t *)(UART2_BASE_ADDR + 0x28))
751 #define U2TER (*(reg32_t *)(UART2_BASE_ADDR + 0x30))
753 /* Universal Asynchronous Receiver Transmitter 3 (UART3) */
754 #define UART3_BASE_ADDR 0xE007C000
755 #define U3RBR (*(reg32_t *)(UART3_BASE_ADDR + 0x00))
756 #define U3THR (*(reg32_t *)(UART3_BASE_ADDR + 0x00))
757 #define U3DLL (*(reg32_t *)(UART3_BASE_ADDR + 0x00))
758 #define U3DLM (*(reg32_t *)(UART3_BASE_ADDR + 0x04))
759 #define U3IER (*(reg32_t *)(UART3_BASE_ADDR + 0x04))
760 #define U3IIR (*(reg32_t *)(UART3_BASE_ADDR + 0x08))
761 #define U3FCR (*(reg32_t *)(UART3_BASE_ADDR + 0x08))
762 #define U3LCR (*(reg32_t *)(UART3_BASE_ADDR + 0x0C))
763 #define U3LSR (*(reg32_t *)(UART3_BASE_ADDR + 0x14))
764 #define U3SCR (*(reg32_t *)(UART3_BASE_ADDR + 0x1C))
765 #define U3ACR (*(reg32_t *)(UART3_BASE_ADDR + 0x20))
766 #define U3ICR (*(reg32_t *)(UART3_BASE_ADDR + 0x24))
767 #define U3FDR (*(reg32_t *)(UART3_BASE_ADDR + 0x28))
768 #define U3TER (*(reg32_t *)(UART3_BASE_ADDR + 0x30))
770 /* I2C Interface 0 */
771 #define I2C0_BASE_ADDR 0xE001C000
772 #define I20CONSET (*(reg32_t *)(I2C0_BASE_ADDR + 0x00))
773 #define I20STAT (*(reg32_t *)(I2C0_BASE_ADDR + 0x04))
774 #define I20DAT (*(reg32_t *)(I2C0_BASE_ADDR + 0x08))
775 #define I20ADR (*(reg32_t *)(I2C0_BASE_ADDR + 0x0C))
776 #define I20SCLH (*(reg32_t *)(I2C0_BASE_ADDR + 0x10))
777 #define I20SCLL (*(reg32_t *)(I2C0_BASE_ADDR + 0x14))
778 #define I20CONCLR (*(reg32_t *)(I2C0_BASE_ADDR + 0x18))
780 /* I2C Interface 1 */
781 #define I2C1_BASE_ADDR 0xE005C000
782 #define I21CONSET (*(reg32_t *)(I2C1_BASE_ADDR + 0x00))
783 #define I21STAT (*(reg32_t *)(I2C1_BASE_ADDR + 0x04))
784 #define I21DAT (*(reg32_t *)(I2C1_BASE_ADDR + 0x08))
785 #define I21ADR (*(reg32_t *)(I2C1_BASE_ADDR + 0x0C))
786 #define I21SCLH (*(reg32_t *)(I2C1_BASE_ADDR + 0x10))
787 #define I21SCLL (*(reg32_t *)(I2C1_BASE_ADDR + 0x14))
788 #define I21CONCLR (*(reg32_t *)(I2C1_BASE_ADDR + 0x18))
790 /* I2C Interface 2 */
791 #define I2C2_BASE_ADDR 0xE0080000
792 #define I22CONSET (*(reg32_t *)(I2C2_BASE_ADDR + 0x00))
793 #define I22STAT (*(reg32_t *)(I2C2_BASE_ADDR + 0x04))
794 #define I22DAT (*(reg32_t *)(I2C2_BASE_ADDR + 0x08))
795 #define I22ADR (*(reg32_t *)(I2C2_BASE_ADDR + 0x0C))
796 #define I22SCLH (*(reg32_t *)(I2C2_BASE_ADDR + 0x10))
797 #define I22SCLL (*(reg32_t *)(I2C2_BASE_ADDR + 0x14))
798 #define I22CONCLR (*(reg32_t *)(I2C2_BASE_ADDR + 0x18))
801 #define I2C_CONSET_OFF 0x00
802 #define I2C_STAT_OFF 0x04
803 #define I2C_DAT_OFF 0x08
804 #define I2C_ADR_OFF 0x0C
805 #define I2C_SCLH_OFF 0x10
806 #define I2C_SCLL_OFF 0x14
807 #define I2C_CONCLR_OFF 0x18
809 /* I2C register definition Clear */
810 #define I2CON_I2ENC 6 // I2C interface Disable bit
811 #define I2CON_STAC 5 // START flag Clear bit
812 #define I2CON_SIC 3 // I2C interrupt Clear bit
813 #define I2CON_AAC 2 // Assert acknowledge Clear bit
815 /* I2C register definition Set */
816 #define I2CON_I2EN 6 // I2C interface enable
817 #define I2CON_STA 5 // START flag Clear bit
818 #define I2CON_STO 4 // STOP flag Clear bit
819 #define I2CON_SI 3 // I2C interrupt Clear bit
820 #define I2CON_AA 2 // Assert acknowledge Clear bit
822 /* I2C Status codes */
823 #define I2C_STAT_ERROR 0x00
824 #define I2C_STAT_UNKNOW 0xF8
825 #define I2C_STAT_SEND 0x08
826 #define I2C_STAT_RESEND 0x10
827 #define I2C_STAT_SLAW_ACK 0x18
828 #define I2C_STAT_SLAW_NACK 0x20
829 #define I2C_STAT_SLAR_ACK 0x40
830 #define I2C_STAT_SLAR_NACK 0x48
831 #define I2C_STAT_DATA_ACK 0x28
832 #define I2C_STAT_DATA_NACK 0x30
833 #define I2C_STAT_RDATA_ACK 0x50
834 #define I2C_STAT_RDATA_NACK 0x58
835 #define I2C_STAT_ARB_LOST 0x38
837 #define I2C0_PCLK_MASK 0xC000
838 #define I2C0_PCLK_DIV8 0xC000
839 #define I2C0_PCLK_DIV4 0x4000
840 #define I2C1_PCLK_MASK 0x00C0
841 #define I2C1_PCLK_DIV8 0x00C0
842 #define I2C1_PCLK_DIV4 0x0040
843 #define I2C2_PCLK_MASK 0x300000
844 #define I2C2_PCLK_DIV8 0x300000
845 #define I2C2_PCLK_DIV4 0x100000
847 /* I2C pins defines */
848 #define I2C0_PINSEL_MASK 0x3C00000
849 #define I2C0_PINSEL 0x1400000
850 #define I2C1_PINSEL_MASK 0x000000F
851 #define I2C1_PINSEL 0x000000F
852 #define I2C2_PINSEL_MASK 0x0F00000
853 #define I2C2_PINSEL 0x0A00000
855 /* SPI0 (Serial Peripheral Interface 0) */
856 #define SPI0_BASE_ADDR 0xE0020000
857 #define S0SPCR (*(reg32_t *)(SPI0_BASE_ADDR + 0x00))
858 #define S0SPSR (*(reg32_t *)(SPI0_BASE_ADDR + 0x04))
859 #define S0SPDR (*(reg32_t *)(SPI0_BASE_ADDR + 0x08))
860 #define S0SPCCR (*(reg32_t *)(SPI0_BASE_ADDR + 0x0C))
861 #define S0SPINT (*(reg32_t *)(SPI0_BASE_ADDR + 0x1C))
863 /* SSP0 Controller */
864 #define SSP0_BASE_ADDR 0xE0068000
865 #define SSP0CR0 (*(reg32_t *)(SSP0_BASE_ADDR + 0x00))
866 #define SSP0CR1 (*(reg32_t *)(SSP0_BASE_ADDR + 0x04))
867 #define SSP0DR (*(reg32_t *)(SSP0_BASE_ADDR + 0x08))
868 #define SSP0SR (*(reg32_t *)(SSP0_BASE_ADDR + 0x0C))
869 #define SSP0CPSR (*(reg32_t *)(SSP0_BASE_ADDR + 0x10))
870 #define SSP0IMSC (*(reg32_t *)(SSP0_BASE_ADDR + 0x14))
871 #define SSP0RIS (*(reg32_t *)(SSP0_BASE_ADDR + 0x18))
872 #define SSP0MIS (*(reg32_t *)(SSP0_BASE_ADDR + 0x1C))
873 #define SSP0ICR (*(reg32_t *)(SSP0_BASE_ADDR + 0x20))
874 #define SSP0DMACR (*(reg32_t *)(SSP0_BASE_ADDR + 0x24))
876 /* SSP1 Controller */
877 #define SSP1_BASE_ADDR 0xE0030000
878 #define SSP1CR0 (*(reg32_t *)(SSP1_BASE_ADDR + 0x00))
879 #define SSP1CR1 (*(reg32_t *)(SSP1_BASE_ADDR + 0x04))
880 #define SSP1DR (*(reg32_t *)(SSP1_BASE_ADDR + 0x08))
881 #define SSP1SR (*(reg32_t *)(SSP1_BASE_ADDR + 0x0C))
882 #define SSP1CPSR (*(reg32_t *)(SSP1_BASE_ADDR + 0x10))
883 #define SSP1IMSC (*(reg32_t *)(SSP1_BASE_ADDR + 0x14))
884 #define SSP1RIS (*(reg32_t *)(SSP1_BASE_ADDR + 0x18))
885 #define SSP1MIS (*(reg32_t *)(SSP1_BASE_ADDR + 0x1C))
886 #define SSP1ICR (*(reg32_t *)(SSP1_BASE_ADDR + 0x20))
887 #define SSP1DMACR (*(reg32_t *)(SSP1_BASE_ADDR + 0x24))
890 /* Real Time Clock */
891 #define RTC_BASE_ADDR 0xE0024000
892 #define RTC_ILR (*(reg32_t *)(RTC_BASE_ADDR + 0x00))
893 #define RTC_CTC (*(reg32_t *)(RTC_BASE_ADDR + 0x04))
894 #define RTC_CCR (*(reg32_t *)(RTC_BASE_ADDR + 0x08))
895 #define RTC_CIIR (*(reg32_t *)(RTC_BASE_ADDR + 0x0C))
896 #define RTC_AMR (*(reg32_t *)(RTC_BASE_ADDR + 0x10))
897 #define RTC_CTIME0 (*(reg32_t *)(RTC_BASE_ADDR + 0x14))
898 #define RTC_CTIME1 (*(reg32_t *)(RTC_BASE_ADDR + 0x18))
899 #define RTC_CTIME2 (*(reg32_t *)(RTC_BASE_ADDR + 0x1C))
900 #define RTC_SEC (*(reg32_t *)(RTC_BASE_ADDR + 0x20))
901 #define RTC_MIN (*(reg32_t *)(RTC_BASE_ADDR + 0x24))
902 #define RTC_HOUR (*(reg32_t *)(RTC_BASE_ADDR + 0x28))
903 #define RTC_DOM (*(reg32_t *)(RTC_BASE_ADDR + 0x2C))
904 #define RTC_DOW (*(reg32_t *)(RTC_BASE_ADDR + 0x30))
905 #define RTC_DOY (*(reg32_t *)(RTC_BASE_ADDR + 0x34))
906 #define RTC_MONTH (*(reg32_t *)(RTC_BASE_ADDR + 0x38))
907 #define RTC_YEAR (*(reg32_t *)(RTC_BASE_ADDR + 0x3C))
908 #define RTC_CISS (*(reg32_t *)(RTC_BASE_ADDR + 0x40))
909 #define RTC_ALSEC (*(reg32_t *)(RTC_BASE_ADDR + 0x60))
910 #define RTC_ALMIN (*(reg32_t *)(RTC_BASE_ADDR + 0x64))
911 #define RTC_ALHOUR (*(reg32_t *)(RTC_BASE_ADDR + 0x68))
912 #define RTC_ALDOM (*(reg32_t *)(RTC_BASE_ADDR + 0x6C))
913 #define RTC_ALDOW (*(reg32_t *)(RTC_BASE_ADDR + 0x70))
914 #define RTC_ALDOY (*(reg32_t *)(RTC_BASE_ADDR + 0x74))
915 #define RTC_ALMON (*(reg32_t *)(RTC_BASE_ADDR + 0x78))
916 #define RTC_ALYEAR (*(reg32_t *)(RTC_BASE_ADDR + 0x7C))
917 #define RTC_PREINT (*(reg32_t *)(RTC_BASE_ADDR + 0x80))
918 #define RTC_PREFRAC (*(reg32_t *)(RTC_BASE_ADDR + 0x84))
921 /* A/D Converter 0 (AD0) */
922 #define AD0_BASE_ADDR 0xE0034000
923 #define AD0CR (*(reg32_t *)(AD0_BASE_ADDR + 0x00))
924 #define AD0GDR (*(reg32_t *)(AD0_BASE_ADDR + 0x04))
925 #define AD0INTEN (*(reg32_t *)(AD0_BASE_ADDR + 0x0C))
926 #define AD0DR0 (*(reg32_t *)(AD0_BASE_ADDR + 0x10))
927 #define AD0DR1 (*(reg32_t *)(AD0_BASE_ADDR + 0x14))
928 #define AD0DR2 (*(reg32_t *)(AD0_BASE_ADDR + 0x18))
929 #define AD0DR3 (*(reg32_t *)(AD0_BASE_ADDR + 0x1C))
930 #define AD0DR4 (*(reg32_t *)(AD0_BASE_ADDR + 0x20))
931 #define AD0DR5 (*(reg32_t *)(AD0_BASE_ADDR + 0x24))
932 #define AD0DR6 (*(reg32_t *)(AD0_BASE_ADDR + 0x28))
933 #define AD0DR7 (*(reg32_t *)(AD0_BASE_ADDR + 0x2C))
934 #define AD0STAT (*(reg32_t *)(AD0_BASE_ADDR + 0x30))
938 #define DAC_BASE_ADDR 0xE006C000
939 #define DACR (*(reg32_t *)(DAC_BASE_ADDR + 0x00))
943 #define WDG_BASE_ADDR 0xE0000000
944 #define WDMOD (*(reg32_t *)(WDG_BASE_ADDR + 0x00))
945 #define WDTC (*(reg32_t *)(WDG_BASE_ADDR + 0x04))
946 #define WDFEED (*(reg32_t *)(WDG_BASE_ADDR + 0x08))
947 #define WDTV (*(reg32_t *)(WDG_BASE_ADDR + 0x0C))
948 #define WDCLKSEL (*(reg32_t *)(WDG_BASE_ADDR + 0x10))
950 /* CAN CONTROLLERS AND ACCEPTANCE FILTER */
951 #define CAN_ACCEPT_BASE_ADDR 0xE003C000
952 #define CAN_AFMR (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x00))
953 #define CAN_SFF_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x04))
954 #define CAN_SFF_GRP_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x08))
955 #define CAN_EFF_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x0C))
956 #define CAN_EFF_GRP_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x10))
957 #define CAN_EOT (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x14))
958 #define CAN_LUT_ERR_ADR (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x18))
959 #define CAN_LUT_ERR (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x1C))
961 #define CAN_CENTRAL_BASE_ADDR 0xE0040000
962 #define CAN_TX_SR (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x00))
963 #define CAN_RX_SR (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x04))
964 #define CAN_MSR (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x08))
966 #define CAN1_BASE_ADDR 0xE0044000
967 #define CAN1MOD (*(reg32_t *)(CAN1_BASE_ADDR + 0x00))
968 #define CAN1CMR (*(reg32_t *)(CAN1_BASE_ADDR + 0x04))
969 #define CAN1GSR (*(reg32_t *)(CAN1_BASE_ADDR + 0x08))
970 #define CAN1ICR (*(reg32_t *)(CAN1_BASE_ADDR + 0x0C))
971 #define CAN1IER (*(reg32_t *)(CAN1_BASE_ADDR + 0x10))
972 #define CAN1BTR (*(reg32_t *)(CAN1_BASE_ADDR + 0x14))
973 #define CAN1EWL (*(reg32_t *)(CAN1_BASE_ADDR + 0x18))
974 #define CAN1SR (*(reg32_t *)(CAN1_BASE_ADDR + 0x1C))
975 #define CAN1RFS (*(reg32_t *)(CAN1_BASE_ADDR + 0x20))
976 #define CAN1RID (*(reg32_t *)(CAN1_BASE_ADDR + 0x24))
977 #define CAN1RDA (*(reg32_t *)(CAN1_BASE_ADDR + 0x28))
978 #define CAN1RDB (*(reg32_t *)(CAN1_BASE_ADDR + 0x2C))
980 #define CAN1TFI1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x30))
981 #define CAN1TID1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x34))
982 #define CAN1TDA1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x38))
983 #define CAN1TDB1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x3C))
984 #define CAN1TFI2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x40))
985 #define CAN1TID2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x44))
986 #define CAN1TDA2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x48))
987 #define CAN1TDB2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x4C))
988 #define CAN1TFI3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x50))
989 #define CAN1TID3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x54))
990 #define CAN1TDA3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x58))
991 #define CAN1TDB3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x5C))
993 #define CAN2_BASE_ADDR 0xE0048000
994 #define CAN2MOD (*(reg32_t *)(CAN2_BASE_ADDR + 0x00))
995 #define CAN2CMR (*(reg32_t *)(CAN2_BASE_ADDR + 0x04))
996 #define CAN2GSR (*(reg32_t *)(CAN2_BASE_ADDR + 0x08))
997 #define CAN2ICR (*(reg32_t *)(CAN2_BASE_ADDR + 0x0C))
998 #define CAN2IER (*(reg32_t *)(CAN2_BASE_ADDR + 0x10))
999 #define CAN2BTR (*(reg32_t *)(CAN2_BASE_ADDR + 0x14))
1000 #define CAN2EWL (*(reg32_t *)(CAN2_BASE_ADDR + 0x18))
1001 #define CAN2SR (*(reg32_t *)(CAN2_BASE_ADDR + 0x1C))
1002 #define CAN2RFS (*(reg32_t *)(CAN2_BASE_ADDR + 0x20))
1003 #define CAN2RID (*(reg32_t *)(CAN2_BASE_ADDR + 0x24))
1004 #define CAN2RDA (*(reg32_t *)(CAN2_BASE_ADDR + 0x28))
1005 #define CAN2RDB (*(reg32_t *)(CAN2_BASE_ADDR + 0x2C))
1007 #define CAN2TFI1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x30))
1008 #define CAN2TID1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x34))
1009 #define CAN2TDA1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x38))
1010 #define CAN2TDB1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x3C))
1011 #define CAN2TFI2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x40))
1012 #define CAN2TID2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x44))
1013 #define CAN2TDA2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x48))
1014 #define CAN2TDB2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x4C))
1015 #define CAN2TFI3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x50))
1016 #define CAN2TID3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x54))
1017 #define CAN2TDA3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x58))
1018 #define CAN2TDB3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x5C))
1021 /* MultiMedia Card Interface(MCI) Controller */
1022 #define MCI_BASE_ADDR 0xE008C000
1023 #define MCI_POWER (*(reg32_t *)(MCI_BASE_ADDR + 0x00))
1024 #define MCI_CLOCK (*(reg32_t *)(MCI_BASE_ADDR + 0x04))
1025 #define MCI_ARGUMENT (*(reg32_t *)(MCI_BASE_ADDR + 0x08))
1026 #define MCI_COMMAND (*(reg32_t *)(MCI_BASE_ADDR + 0x0C))
1027 #define MCI_RESP_CMD (*(reg32_t *)(MCI_BASE_ADDR + 0x10))
1028 #define MCI_RESP0 (*(reg32_t *)(MCI_BASE_ADDR + 0x14))
1029 #define MCI_RESP1 (*(reg32_t *)(MCI_BASE_ADDR + 0x18))
1030 #define MCI_RESP2 (*(reg32_t *)(MCI_BASE_ADDR + 0x1C))
1031 #define MCI_RESP3 (*(reg32_t *)(MCI_BASE_ADDR + 0x20))
1032 #define MCI_DATA_TMR (*(reg32_t *)(MCI_BASE_ADDR + 0x24))
1033 #define MCI_DATA_LEN (*(reg32_t *)(MCI_BASE_ADDR + 0x28))
1034 #define MCI_DATA_CTRL (*(reg32_t *)(MCI_BASE_ADDR + 0x2C))
1035 #define MCI_DATA_CNT (*(reg32_t *)(MCI_BASE_ADDR + 0x30))
1036 #define MCI_STATUS (*(reg32_t *)(MCI_BASE_ADDR + 0x34))
1037 #define MCI_CLEAR (*(reg32_t *)(MCI_BASE_ADDR + 0x38))
1038 #define MCI_MASK0 (*(reg32_t *)(MCI_BASE_ADDR + 0x3C))
1039 #define MCI_MASK1 (*(reg32_t *)(MCI_BASE_ADDR + 0x40))
1040 #define MCI_FIFO_CNT (*(reg32_t *)(MCI_BASE_ADDR + 0x48))
1041 #define MCI_FIFO (*(reg32_t *)(MCI_BASE_ADDR + 0x80))
1044 /* I2S Interface Controller (I2S) */
1045 #define I2S_BASE_ADDR 0xE0088000
1046 #define I2S_DAO (*(reg32_t *)(I2S_BASE_ADDR + 0x00))
1047 #define I2S_DAI (*(reg32_t *)(I2S_BASE_ADDR + 0x04))
1048 #define I2S_TX_FIFO (*(reg32_t *)(I2S_BASE_ADDR + 0x08))
1049 #define I2S_RX_FIFO (*(reg32_t *)(I2S_BASE_ADDR + 0x0C))
1050 #define I2S_STATE (*(reg32_t *)(I2S_BASE_ADDR + 0x10))
1051 #define I2S_DMA1 (*(reg32_t *)(I2S_BASE_ADDR + 0x14))
1052 #define I2S_DMA2 (*(reg32_t *)(I2S_BASE_ADDR + 0x18))
1053 #define I2S_IRQ (*(reg32_t *)(I2S_BASE_ADDR + 0x1C))
1054 #define I2S_TXRATE (*(reg32_t *)(I2S_BASE_ADDR + 0x20))
1055 #define I2S_RXRATE (*(reg32_t *)(I2S_BASE_ADDR + 0x24))
1058 /* General-purpose DMA Controller */
1059 #define DMA_BASE_ADDR 0xFFE04000
1060 #define GPDMA_INT_STAT (*(reg32_t *)(DMA_BASE_ADDR + 0x000))
1061 #define GPDMA_INT_TCSTAT (*(reg32_t *)(DMA_BASE_ADDR + 0x004))
1062 #define GPDMA_INT_TCCLR (*(reg32_t *)(DMA_BASE_ADDR + 0x008))
1063 #define GPDMA_INT_ERR_STAT (*(reg32_t *)(DMA_BASE_ADDR + 0x00C))
1064 #define GPDMA_INT_ERR_CLR (*(reg32_t *)(DMA_BASE_ADDR + 0x010))
1065 #define GPDMA_RAW_INT_TCSTAT (*(reg32_t *)(DMA_BASE_ADDR + 0x014))
1066 #define GPDMA_RAW_INT_ERR_STAT (*(reg32_t *)(DMA_BASE_ADDR + 0x018))
1067 #define GPDMA_ENABLED_CHNS (*(reg32_t *)(DMA_BASE_ADDR + 0x01C))
1068 #define GPDMA_SOFT_BREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x020))
1069 #define GPDMA_SOFT_SREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x024))
1070 #define GPDMA_SOFT_LBREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x028))
1071 #define GPDMA_SOFT_LSREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x02C))
1072 #define GPDMA_CONFIG (*(reg32_t *)(DMA_BASE_ADDR + 0x030))
1073 #define GPDMA_SYNC (*(reg32_t *)(DMA_BASE_ADDR + 0x034))
1075 /* DMA channel 0 registers */
1076 #define GPDMA_CH0_SRC (*(reg32_t *)(DMA_BASE_ADDR + 0x100))
1077 #define GPDMA_CH0_DEST (*(reg32_t *)(DMA_BASE_ADDR + 0x104))
1078 #define GPDMA_CH0_LLI (*(reg32_t *)(DMA_BASE_ADDR + 0x108))
1079 #define GPDMA_CH0_CTRL (*(reg32_t *)(DMA_BASE_ADDR + 0x10C))
1080 #define GPDMA_CH0_CFG (*(reg32_t *)(DMA_BASE_ADDR + 0x110))
1082 /* DMA channel 1 registers */
1083 #define GPDMA_CH1_SRC (*(reg32_t *)(DMA_BASE_ADDR + 0x120))
1084 #define GPDMA_CH1_DEST (*(reg32_t *)(DMA_BASE_ADDR + 0x124))
1085 #define GPDMA_CH1_LLI (*(reg32_t *)(DMA_BASE_ADDR + 0x128))
1086 #define GPDMA_CH1_CTRL (*(reg32_t *)(DMA_BASE_ADDR + 0x12C))
1087 #define GPDMA_CH1_CFG (*(reg32_t *)(DMA_BASE_ADDR + 0x130))
1090 /* USB Controller */
1091 #define USB_INT_BASE_ADDR 0xE01FC1C0
1092 #define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */
1094 #define USB_INT_STAT (*(reg32_t *)(USB_INT_BASE_ADDR + 0x00))
1096 /* USB Device Interrupt Registers */
1097 #define DEV_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x00))
1098 #define DEV_INT_EN (*(reg32_t *)(USB_BASE_ADDR + 0x04))
1099 #define DEV_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0x08))
1100 #define DEV_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0x0C))
1101 #define DEV_INT_PRIO (*(reg32_t *)(USB_BASE_ADDR + 0x2C))
1103 /* USB Device Endpoint Interrupt Registers */
1104 #define EP_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x30))
1105 #define EP_INT_EN (*(reg32_t *)(USB_BASE_ADDR + 0x34))
1106 #define EP_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0x38))
1107 #define EP_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0x3C))
1108 #define EP_INT_PRIO (*(reg32_t *)(USB_BASE_ADDR + 0x40))
1110 /* USB Device Endpoint Realization Registers */
1111 #define REALIZE_EP (*(reg32_t *)(USB_BASE_ADDR + 0x44))
1112 #define EP_INDEX (*(reg32_t *)(USB_BASE_ADDR + 0x48))
1113 #define MAXPACKET_SIZE (*(reg32_t *)(USB_BASE_ADDR + 0x4C))
1115 /* USB Device Command Reagisters */
1116 #define CMD_CODE (*(reg32_t *)(USB_BASE_ADDR + 0x10))
1117 #define CMD_DATA (*(reg32_t *)(USB_BASE_ADDR + 0x14))
1119 /* USB Device Data Transfer Registers */
1120 #define RX_DATA (*(reg32_t *)(USB_BASE_ADDR + 0x18))
1121 #define TX_DATA (*(reg32_t *)(USB_BASE_ADDR + 0x1C))
1122 #define RX_PLENGTH (*(reg32_t *)(USB_BASE_ADDR + 0x20))
1123 #define TX_PLENGTH (*(reg32_t *)(USB_BASE_ADDR + 0x24))
1124 #define USB_CTRL (*(reg32_t *)(USB_BASE_ADDR + 0x28))
1126 /* USB Device DMA Registers */
1127 #define DMA_REQ_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x50))
1128 #define DMA_REQ_CLR (*(reg32_t *)(USB_BASE_ADDR + 0x54))
1129 #define DMA_REQ_SET (*(reg32_t *)(USB_BASE_ADDR + 0x58))
1130 #define UDCA_HEAD (*(reg32_t *)(USB_BASE_ADDR + 0x80))
1131 #define EP_DMA_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x84))
1132 #define EP_DMA_EN (*(reg32_t *)(USB_BASE_ADDR + 0x88))
1133 #define EP_DMA_DIS (*(reg32_t *)(USB_BASE_ADDR + 0x8C))
1134 #define DMA_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x90))
1135 #define DMA_INT_EN (*(reg32_t *)(USB_BASE_ADDR + 0x94))
1136 #define EOT_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0xA0))
1137 #define EOT_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0xA4))
1138 #define EOT_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0xA8))
1139 #define NDD_REQ_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0xAC))
1140 #define NDD_REQ_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0xB0))
1141 #define NDD_REQ_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0xB4))
1142 #define SYS_ERR_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0xB8))
1143 #define SYS_ERR_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0xBC))
1144 #define SYS_ERR_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0xC0))
1146 /* USB Host and OTG registers are for LPC24xx only */
1147 /* USB Host Controller */
1148 #define USBHC_BASE_ADDR 0xFFE0C000
1149 #define HC_REVISION (*(reg32_t *)(USBHC_BASE_ADDR + 0x00))
1150 #define HC_CONTROL (*(reg32_t *)(USBHC_BASE_ADDR + 0x04))
1151 #define HC_CMD_STAT (*(reg32_t *)(USBHC_BASE_ADDR + 0x08))
1152 #define HC_INT_STAT (*(reg32_t *)(USBHC_BASE_ADDR + 0x0C))
1153 #define HC_INT_EN (*(reg32_t *)(USBHC_BASE_ADDR + 0x10))
1154 #define HC_INT_DIS (*(reg32_t *)(USBHC_BASE_ADDR + 0x14))
1155 #define HC_HCCA (*(reg32_t *)(USBHC_BASE_ADDR + 0x18))
1156 #define HC_PERIOD_CUR_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x1C))
1157 #define HC_CTRL_HEAD_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x20))
1158 #define HC_CTRL_CUR_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x24))
1159 #define HC_BULK_HEAD_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x28))
1160 #define HC_BULK_CUR_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x2C))
1161 #define HC_DONE_HEAD (*(reg32_t *)(USBHC_BASE_ADDR + 0x30))
1162 #define HC_FM_INTERVAL (*(reg32_t *)(USBHC_BASE_ADDR + 0x34))
1163 #define HC_FM_REMAINING (*(reg32_t *)(USBHC_BASE_ADDR + 0x38))
1164 #define HC_FM_NUMBER (*(reg32_t *)(USBHC_BASE_ADDR + 0x3C))
1165 #define HC_PERIOD_START (*(reg32_t *)(USBHC_BASE_ADDR + 0x40))
1166 #define HC_LS_THRHLD (*(reg32_t *)(USBHC_BASE_ADDR + 0x44))
1167 #define HC_RH_DESCA (*(reg32_t *)(USBHC_BASE_ADDR + 0x48))
1168 #define HC_RH_DESCB (*(reg32_t *)(USBHC_BASE_ADDR + 0x4C))
1169 #define HC_RH_STAT (*(reg32_t *)(USBHC_BASE_ADDR + 0x50))
1170 #define HC_RH_PORT_STAT1 (*(reg32_t *)(USBHC_BASE_ADDR + 0x54))
1171 #define HC_RH_PORT_STAT2 (*(reg32_t *)(USBHC_BASE_ADDR + 0x58))
1173 /* USB OTG Controller */
1174 #define USBOTG_BASE_ADDR 0xFFE0C100
1175 #define OTG_INT_STAT (*(reg32_t *)(USBOTG_BASE_ADDR + 0x00))
1176 #define OTG_INT_EN (*(reg32_t *)(USBOTG_BASE_ADDR + 0x04))
1177 #define OTG_INT_SET (*(reg32_t *)(USBOTG_BASE_ADDR + 0x08))
1178 #define OTG_INT_CLR (*(reg32_t *)(USBOTG_BASE_ADDR + 0x0C))
1179 /* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */
1180 #define OTG_STAT_CTRL (*(reg32_t *)(USBOTG_BASE_ADDR + 0x10))
1181 #define OTG_TIMER (*(reg32_t *)(USBOTG_BASE_ADDR + 0x14))
1183 #define USBOTG_I2C_BASE_ADDR 0xFFE0C300
1184 #define OTG_I2C_RX (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x00))
1185 #define OTG_I2C_TX (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x00))
1186 #define OTG_I2C_STS (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x04))
1187 #define OTG_I2C_CTL (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x08))
1188 #define OTG_I2C_CLKHI (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x0C))
1189 #define OTG_I2C_CLKLO (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x10))
1191 /* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are
1192 OTG_CLK_CTRL and OTG_CLK_STAT respectively. */
1193 #define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0
1194 #define OTG_CLK_CTRL (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x04))
1195 #define OTG_CLK_STAT (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x08))
1197 /* Note: below three register name convention is for LPC23xx USB device only, match
1198 with the spec. update in USB Device Section. */
1199 #define USBPortSel (*(reg32_t *)(USBOTG_BASE_ADDR + 0x10))
1200 #define USBClkCtrl (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x04))
1201 #define USBClkSt (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x08))
1203 /* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
1204 #define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */
1205 #define MAC_MAC1 (*(reg32_t *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
1206 #define MAC_MAC2 (*(reg32_t *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
1207 #define MAC_IPGT (*(reg32_t *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
1208 #define MAC_IPGR (*(reg32_t *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */
1209 #define MAC_CLRT (*(reg32_t *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */
1210 #define MAC_MAXF (*(reg32_t *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */
1211 #define MAC_SUPP (*(reg32_t *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */
1212 #define MAC_TEST (*(reg32_t *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */
1213 #define MAC_MCFG (*(reg32_t *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */
1214 #define MAC_MCMD (*(reg32_t *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */
1215 #define MAC_MADR (*(reg32_t *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */
1216 #define MAC_MWTD (*(reg32_t *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
1217 #define MAC_MRDD (*(reg32_t *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
1218 #define MAC_MIND (*(reg32_t *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */
1220 #define MAC_SA0 (*(reg32_t *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */
1221 #define MAC_SA1 (*(reg32_t *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */
1222 #define MAC_SA2 (*(reg32_t *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */
1224 #define MAC_COMMAND (*(reg32_t *)(MAC_BASE_ADDR + 0x100)) /* Command reg */
1225 #define MAC_STATUS (*(reg32_t *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */
1226 #define MAC_RXDESCRIPTOR (*(reg32_t *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */
1227 #define MAC_RXSTATUS (*(reg32_t *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */
1228 #define MAC_RXDESCRIPTORNUM (*(reg32_t *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */
1229 #define MAC_RXPRODUCEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */
1230 #define MAC_RXCONSUMEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */
1231 #define MAC_TXDESCRIPTOR (*(reg32_t *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */
1232 #define MAC_TXSTATUS (*(reg32_t *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */
1233 #define MAC_TXDESCRIPTORNUM (*(reg32_t *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */
1234 #define MAC_TXPRODUCEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */
1235 #define MAC_TXCONSUMEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */
1237 #define MAC_TSV0 (*(reg32_t *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */
1238 #define MAC_TSV1 (*(reg32_t *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */
1239 #define MAC_RSV (*(reg32_t *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */
1241 #define MAC_FLOWCONTROLCNT (*(reg32_t *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */
1242 #define MAC_FLOWCONTROLSTS (*(reg32_t *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */
1244 #define MAC_RXFILTERCTRL (*(reg32_t *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */
1245 #define MAC_RXFILTERWOLSTS (*(reg32_t *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */
1246 #define MAC_RXFILTERWOLCLR (*(reg32_t *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */
1248 #define MAC_HASHFILTERL (*(reg32_t *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */
1249 #define MAC_HASHFILTERH (*(reg32_t *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */
1251 #define MAC_INTSTATUS (*(reg32_t *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */
1252 #define MAC_INTENABLE (*(reg32_t *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */
1253 #define MAC_INTCLEAR (*(reg32_t *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */
1254 #define MAC_INTSET (*(reg32_t *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */
1256 #define MAC_POWERDOWN (*(reg32_t *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */
1257 #define MAC_MODULEID (*(reg32_t *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
1266 #define INT_UART2 28
1267 #define INT_UART3 29
1269 #endif /* LPC23XX_H */