4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2010 Develer S.r.l. (http://www.develer.com/)
33 * \author Francesco Sacchi <batt@develer.com>
35 * LPC23xx I/O registers.
41 #include <cfg/compiler.h>
43 /* Vectored Interrupt Controller (VIC) */
44 #define VIC_BASE_ADDR 0xFFFFF000
45 #define VICIRQStatus (*(reg32_t *)(VIC_BASE_ADDR + 0x000))
46 #define VICFIQStatus (*(reg32_t *)(VIC_BASE_ADDR + 0x004))
47 #define VICRawIntr (*(reg32_t *)(VIC_BASE_ADDR + 0x008))
48 #define VICIntSelect (*(reg32_t *)(VIC_BASE_ADDR + 0x00C))
49 #define VICIntEnable (*(reg32_t *)(VIC_BASE_ADDR + 0x010))
50 #define VICIntEnClr (*(reg32_t *)(VIC_BASE_ADDR + 0x014))
51 #define VICSoftInt (*(reg32_t *)(VIC_BASE_ADDR + 0x018))
52 #define VICSoftIntClr (*(reg32_t *)(VIC_BASE_ADDR + 0x01C))
53 #define VICProtection (*(reg32_t *)(VIC_BASE_ADDR + 0x020))
54 #define VICSWPrioMask (*(reg32_t *)(VIC_BASE_ADDR + 0x024))
56 #define VICVectAddr0 (*(reg32_t *)(VIC_BASE_ADDR + 0x100))
57 #define VICVectAddr1 (*(reg32_t *)(VIC_BASE_ADDR + 0x104))
58 #define VICVectAddr2 (*(reg32_t *)(VIC_BASE_ADDR + 0x108))
59 #define VICVectAddr3 (*(reg32_t *)(VIC_BASE_ADDR + 0x10C))
60 #define VICVectAddr4 (*(reg32_t *)(VIC_BASE_ADDR + 0x110))
61 #define VICVectAddr5 (*(reg32_t *)(VIC_BASE_ADDR + 0x114))
62 #define VICVectAddr6 (*(reg32_t *)(VIC_BASE_ADDR + 0x118))
63 #define VICVectAddr7 (*(reg32_t *)(VIC_BASE_ADDR + 0x11C))
64 #define VICVectAddr8 (*(reg32_t *)(VIC_BASE_ADDR + 0x120))
65 #define VICVectAddr9 (*(reg32_t *)(VIC_BASE_ADDR + 0x124))
66 #define VICVectAddr10 (*(reg32_t *)(VIC_BASE_ADDR + 0x128))
67 #define VICVectAddr11 (*(reg32_t *)(VIC_BASE_ADDR + 0x12C))
68 #define VICVectAddr12 (*(reg32_t *)(VIC_BASE_ADDR + 0x130))
69 #define VICVectAddr13 (*(reg32_t *)(VIC_BASE_ADDR + 0x134))
70 #define VICVectAddr14 (*(reg32_t *)(VIC_BASE_ADDR + 0x138))
71 #define VICVectAddr15 (*(reg32_t *)(VIC_BASE_ADDR + 0x13C))
72 #define VICVectAddr16 (*(reg32_t *)(VIC_BASE_ADDR + 0x140))
73 #define VICVectAddr17 (*(reg32_t *)(VIC_BASE_ADDR + 0x144))
74 #define VICVectAddr18 (*(reg32_t *)(VIC_BASE_ADDR + 0x148))
75 #define VICVectAddr19 (*(reg32_t *)(VIC_BASE_ADDR + 0x14C))
76 #define VICVectAddr20 (*(reg32_t *)(VIC_BASE_ADDR + 0x150))
77 #define VICVectAddr21 (*(reg32_t *)(VIC_BASE_ADDR + 0x154))
78 #define VICVectAddr22 (*(reg32_t *)(VIC_BASE_ADDR + 0x158))
79 #define VICVectAddr23 (*(reg32_t *)(VIC_BASE_ADDR + 0x15C))
80 #define VICVectAddr24 (*(reg32_t *)(VIC_BASE_ADDR + 0x160))
81 #define VICVectAddr25 (*(reg32_t *)(VIC_BASE_ADDR + 0x164))
82 #define VICVectAddr26 (*(reg32_t *)(VIC_BASE_ADDR + 0x168))
83 #define VICVectAddr27 (*(reg32_t *)(VIC_BASE_ADDR + 0x16C))
84 #define VICVectAddr28 (*(reg32_t *)(VIC_BASE_ADDR + 0x170))
85 #define VICVectAddr29 (*(reg32_t *)(VIC_BASE_ADDR + 0x174))
86 #define VICVectAddr30 (*(reg32_t *)(VIC_BASE_ADDR + 0x178))
87 #define VICVectAddr31 (*(reg32_t *)(VIC_BASE_ADDR + 0x17C))
89 /* The name convention below is from previous LPC2000 family MCUs, in LPC23xx/24xx,
90 these registers are known as "VICVectPriority(x)". */
91 #define VICVectCntl0 (*(reg32_t *)(VIC_BASE_ADDR + 0x200))
92 #define VICVectCntl1 (*(reg32_t *)(VIC_BASE_ADDR + 0x204))
93 #define VICVectCntl2 (*(reg32_t *)(VIC_BASE_ADDR + 0x208))
94 #define VICVectCntl3 (*(reg32_t *)(VIC_BASE_ADDR + 0x20C))
95 #define VICVectCntl4 (*(reg32_t *)(VIC_BASE_ADDR + 0x210))
96 #define VICVectCntl5 (*(reg32_t *)(VIC_BASE_ADDR + 0x214))
97 #define VICVectCntl6 (*(reg32_t *)(VIC_BASE_ADDR + 0x218))
98 #define VICVectCntl7 (*(reg32_t *)(VIC_BASE_ADDR + 0x21C))
99 #define VICVectCntl8 (*(reg32_t *)(VIC_BASE_ADDR + 0x220))
100 #define VICVectCntl9 (*(reg32_t *)(VIC_BASE_ADDR + 0x224))
101 #define VICVectCntl10 (*(reg32_t *)(VIC_BASE_ADDR + 0x228))
102 #define VICVectCntl11 (*(reg32_t *)(VIC_BASE_ADDR + 0x22C))
103 #define VICVectCntl12 (*(reg32_t *)(VIC_BASE_ADDR + 0x230))
104 #define VICVectCntl13 (*(reg32_t *)(VIC_BASE_ADDR + 0x234))
105 #define VICVectCntl14 (*(reg32_t *)(VIC_BASE_ADDR + 0x238))
106 #define VICVectCntl15 (*(reg32_t *)(VIC_BASE_ADDR + 0x23C))
107 #define VICVectCntl16 (*(reg32_t *)(VIC_BASE_ADDR + 0x240))
108 #define VICVectCntl17 (*(reg32_t *)(VIC_BASE_ADDR + 0x244))
109 #define VICVectCntl18 (*(reg32_t *)(VIC_BASE_ADDR + 0x248))
110 #define VICVectCntl19 (*(reg32_t *)(VIC_BASE_ADDR + 0x24C))
111 #define VICVectCntl20 (*(reg32_t *)(VIC_BASE_ADDR + 0x250))
112 #define VICVectCntl21 (*(reg32_t *)(VIC_BASE_ADDR + 0x254))
113 #define VICVectCntl22 (*(reg32_t *)(VIC_BASE_ADDR + 0x258))
114 #define VICVectCntl23 (*(reg32_t *)(VIC_BASE_ADDR + 0x25C))
115 #define VICVectCntl24 (*(reg32_t *)(VIC_BASE_ADDR + 0x260))
116 #define VICVectCntl25 (*(reg32_t *)(VIC_BASE_ADDR + 0x264))
117 #define VICVectCntl26 (*(reg32_t *)(VIC_BASE_ADDR + 0x268))
118 #define VICVectCntl27 (*(reg32_t *)(VIC_BASE_ADDR + 0x26C))
119 #define VICVectCntl28 (*(reg32_t *)(VIC_BASE_ADDR + 0x270))
120 #define VICVectCntl29 (*(reg32_t *)(VIC_BASE_ADDR + 0x274))
121 #define VICVectCntl30 (*(reg32_t *)(VIC_BASE_ADDR + 0x278))
122 #define VICVectCntl31 (*(reg32_t *)(VIC_BASE_ADDR + 0x27C))
124 #define VICVectAddr (*(reg32_t *)(VIC_BASE_ADDR + 0xF00))
127 /* Pin Connect Block */
128 #define PINSEL_BASE_ADDR 0xE002C000
129 #define PINSEL0 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x00))
130 #define PINSEL1 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x04))
131 #define PINSEL2 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x08))
132 #define PINSEL3 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x0C))
133 #define PINSEL4 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x10))
134 #define PINSEL5 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x14))
135 #define PINSEL6 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x18))
136 #define PINSEL7 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x1C))
137 #define PINSEL8 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x20))
138 #define PINSEL9 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x24))
139 #define PINSEL10 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x28))
141 #define PINSEL0_OFF 0x00
142 #define PINSEL1_OFF 0x04
143 #define PINSEL2_OFF 0x08
144 #define PINSEL3_OFF 0x0C
145 #define PINSEL4_OFF 0x10
146 #define PINSEL5_OFF 0x14
147 #define PINSEL6_OFF 0x18
148 #define PINSEL7_OFF 0x1C
149 #define PINSEL8_OFF 0x20
150 #define PINSEL9_OFF 0x24
151 #define PINSEL10_OFF 0x28
153 #define PINMODE0 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x40))
154 #define PINMODE1 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x44))
155 #define PINMODE2 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x48))
156 #define PINMODE3 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x4C))
157 #define PINMODE4 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x50))
158 #define PINMODE5 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x54))
159 #define PINMODE6 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x58))
160 #define PINMODE7 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x5C))
161 #define PINMODE8 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x60))
162 #define PINMODE9 (*(reg32_t *)(PINSEL_BASE_ADDR + 0x64))
164 /* General Purpose Input/Output (GPIO) */
165 #define GPIO_BASE_ADDR 0xE0028000
166 #define IOPIN0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x00))
167 #define IOSET0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x04))
168 #define IODIR0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x08))
169 #define IOCLR0 (*(reg32_t *)(GPIO_BASE_ADDR + 0x0C))
170 #define IOPIN1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x10))
171 #define IOSET1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x14))
172 #define IODIR1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x18))
173 #define IOCLR1 (*(reg32_t *)(GPIO_BASE_ADDR + 0x1C))
175 /* GPIO Interrupt Registers */
176 #define IO0_INT_EN_R (*(reg32_t *)(GPIO_BASE_ADDR + 0x90))
177 #define IO0_INT_EN_F (*(reg32_t *)(GPIO_BASE_ADDR + 0x94))
178 #define IO0_INT_STAT_R (*(reg32_t *)(GPIO_BASE_ADDR + 0x84))
179 #define IO0_INT_STAT_F (*(reg32_t *)(GPIO_BASE_ADDR + 0x88))
180 #define IO0_INT_CLR (*(reg32_t *)(GPIO_BASE_ADDR + 0x8C))
182 #define IO2_INT_EN_R (*(reg32_t *)(GPIO_BASE_ADDR + 0xB0))
183 #define IO2_INT_EN_F (*(reg32_t *)(GPIO_BASE_ADDR + 0xB4))
184 #define IO2_INT_STAT_R (*(reg32_t *)(GPIO_BASE_ADDR + 0xA4))
185 #define IO2_INT_STAT_F (*(reg32_t *)(GPIO_BASE_ADDR + 0xA8))
186 #define IO2_INT_CLR (*(reg32_t *)(GPIO_BASE_ADDR + 0xAC))
188 #define IO_INT_STAT (*(reg32_t *)(GPIO_BASE_ADDR + 0x80))
190 #define PARTCFG_BASE_ADDR 0x3FFF8000
191 #define PARTCFG (*(reg32_t *)(PARTCFG_BASE_ADDR + 0x00))
194 #define FIO_BASE_ADDR 0x3FFFC000
195 #define FIO0DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x00))
196 #define FIO0MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x10))
197 #define FIO0PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x14))
198 #define FIO0SET (*(reg32_t *)(FIO_BASE_ADDR + 0x18))
199 #define FIO0CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x1C))
201 #define FIO1DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x20))
202 #define FIO1MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x30))
203 #define FIO1PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x34))
204 #define FIO1SET (*(reg32_t *)(FIO_BASE_ADDR + 0x38))
205 #define FIO1CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x3C))
207 #define FIO2DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x40))
208 #define FIO2MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x50))
209 #define FIO2PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x54))
210 #define FIO2SET (*(reg32_t *)(FIO_BASE_ADDR + 0x58))
211 #define FIO2CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x5C))
213 #define FIO3DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x60))
214 #define FIO3MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x70))
215 #define FIO3PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x74))
216 #define FIO3SET (*(reg32_t *)(FIO_BASE_ADDR + 0x78))
217 #define FIO3CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x7C))
219 #define FIO4DIR (*(reg32_t *)(FIO_BASE_ADDR + 0x80))
220 #define FIO4MASK (*(reg32_t *)(FIO_BASE_ADDR + 0x90))
221 #define FIO4PIN (*(reg32_t *)(FIO_BASE_ADDR + 0x94))
222 #define FIO4SET (*(reg32_t *)(FIO_BASE_ADDR + 0x98))
223 #define FIO4CLR (*(reg32_t *)(FIO_BASE_ADDR + 0x9C))
225 /* FIOs can be accessed through WORD, HALF-WORD or BYTE. */
226 #define FIO0DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x00))
227 #define FIO1DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x20))
228 #define FIO2DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x40))
229 #define FIO3DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x60))
230 #define FIO4DIR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x80))
232 #define FIO0DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x01))
233 #define FIO1DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x21))
234 #define FIO2DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x41))
235 #define FIO3DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x61))
236 #define FIO4DIR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x81))
238 #define FIO0DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x02))
239 #define FIO1DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x22))
240 #define FIO2DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x42))
241 #define FIO3DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x62))
242 #define FIO4DIR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x82))
244 #define FIO0DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x03))
245 #define FIO1DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x23))
246 #define FIO2DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x43))
247 #define FIO3DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x63))
248 #define FIO4DIR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x83))
250 #define FIO0DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x00))
251 #define FIO1DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x20))
252 #define FIO2DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x40))
253 #define FIO3DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x60))
254 #define FIO4DIRL (*(reg16_t *)(FIO_BASE_ADDR + 0x80))
256 #define FIO0DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x02))
257 #define FIO1DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x22))
258 #define FIO2DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x42))
259 #define FIO3DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x62))
260 #define FIO4DIRU (*(reg16_t *)(FIO_BASE_ADDR + 0x82))
262 #define FIO0MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x10))
263 #define FIO1MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x30))
264 #define FIO2MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x50))
265 #define FIO3MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x70))
266 #define FIO4MASK0 (*(reg8_t *)(FIO_BASE_ADDR + 0x90))
268 #define FIO0MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x11))
269 #define FIO1MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x21))
270 #define FIO2MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x51))
271 #define FIO3MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x71))
272 #define FIO4MASK1 (*(reg8_t *)(FIO_BASE_ADDR + 0x91))
274 #define FIO0MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x12))
275 #define FIO1MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x32))
276 #define FIO2MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x52))
277 #define FIO3MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x72))
278 #define FIO4MASK2 (*(reg8_t *)(FIO_BASE_ADDR + 0x92))
280 #define FIO0MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x13))
281 #define FIO1MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x33))
282 #define FIO2MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x53))
283 #define FIO3MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x73))
284 #define FIO4MASK3 (*(reg8_t *)(FIO_BASE_ADDR + 0x93))
286 #define FIO0MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x10))
287 #define FIO1MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x30))
288 #define FIO2MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x50))
289 #define FIO3MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x70))
290 #define FIO4MASKL (*(reg16_t *)(FIO_BASE_ADDR + 0x90))
292 #define FIO0MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x12))
293 #define FIO1MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x32))
294 #define FIO2MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x52))
295 #define FIO3MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x72))
296 #define FIO4MASKU (*(reg16_t *)(FIO_BASE_ADDR + 0x92))
298 #define FIO0PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x14))
299 #define FIO1PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x34))
300 #define FIO2PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x54))
301 #define FIO3PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x74))
302 #define FIO4PIN0 (*(reg8_t *)(FIO_BASE_ADDR + 0x94))
304 #define FIO0PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x15))
305 #define FIO1PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x25))
306 #define FIO2PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x55))
307 #define FIO3PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x75))
308 #define FIO4PIN1 (*(reg8_t *)(FIO_BASE_ADDR + 0x95))
310 #define FIO0PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x16))
311 #define FIO1PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x36))
312 #define FIO2PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x56))
313 #define FIO3PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x76))
314 #define FIO4PIN2 (*(reg8_t *)(FIO_BASE_ADDR + 0x96))
316 #define FIO0PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x17))
317 #define FIO1PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x37))
318 #define FIO2PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x57))
319 #define FIO3PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x77))
320 #define FIO4PIN3 (*(reg8_t *)(FIO_BASE_ADDR + 0x97))
322 #define FIO0PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x14))
323 #define FIO1PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x34))
324 #define FIO2PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x54))
325 #define FIO3PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x74))
326 #define FIO4PINL (*(reg16_t *)(FIO_BASE_ADDR + 0x94))
328 #define FIO0PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x16))
329 #define FIO1PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x36))
330 #define FIO2PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x56))
331 #define FIO3PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x76))
332 #define FIO4PINU (*(reg16_t *)(FIO_BASE_ADDR + 0x96))
334 #define FIO0SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x18))
335 #define FIO1SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x38))
336 #define FIO2SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x58))
337 #define FIO3SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x78))
338 #define FIO4SET0 (*(reg8_t *)(FIO_BASE_ADDR + 0x98))
340 #define FIO0SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x19))
341 #define FIO1SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x29))
342 #define FIO2SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x59))
343 #define FIO3SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x79))
344 #define FIO4SET1 (*(reg8_t *)(FIO_BASE_ADDR + 0x99))
346 #define FIO0SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x1A))
347 #define FIO1SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x3A))
348 #define FIO2SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x5A))
349 #define FIO3SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x7A))
350 #define FIO4SET2 (*(reg8_t *)(FIO_BASE_ADDR + 0x9A))
352 #define FIO0SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x1B))
353 #define FIO1SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x3B))
354 #define FIO2SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x5B))
355 #define FIO3SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x7B))
356 #define FIO4SET3 (*(reg8_t *)(FIO_BASE_ADDR + 0x9B))
358 #define FIO0SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x18))
359 #define FIO1SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x38))
360 #define FIO2SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x58))
361 #define FIO3SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x78))
362 #define FIO4SETL (*(reg16_t *)(FIO_BASE_ADDR + 0x98))
364 #define FIO0SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x1A))
365 #define FIO1SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x3A))
366 #define FIO2SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x5A))
367 #define FIO3SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x7A))
368 #define FIO4SETU (*(reg16_t *)(FIO_BASE_ADDR + 0x9A))
370 #define FIO0CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x1C))
371 #define FIO1CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x3C))
372 #define FIO2CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x5C))
373 #define FIO3CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x7C))
374 #define FIO4CLR0 (*(reg8_t *)(FIO_BASE_ADDR + 0x9C))
376 #define FIO0CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x1D))
377 #define FIO1CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x2D))
378 #define FIO2CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x5D))
379 #define FIO3CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x7D))
380 #define FIO4CLR1 (*(reg8_t *)(FIO_BASE_ADDR + 0x9D))
382 #define FIO0CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x1E))
383 #define FIO1CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x3E))
384 #define FIO2CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x5E))
385 #define FIO3CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x7E))
386 #define FIO4CLR2 (*(reg8_t *)(FIO_BASE_ADDR + 0x9E))
388 #define FIO0CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x1F))
389 #define FIO1CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x3F))
390 #define FIO2CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x5F))
391 #define FIO3CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x7F))
392 #define FIO4CLR3 (*(reg8_t *)(FIO_BASE_ADDR + 0x9F))
394 #define FIO0CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x1C))
395 #define FIO1CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x3C))
396 #define FIO2CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x5C))
397 #define FIO3CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x7C))
398 #define FIO4CLRL (*(reg16_t *)(FIO_BASE_ADDR + 0x9C))
400 #define FIO0CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x1E))
401 #define FIO1CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x3E))
402 #define FIO2CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x5E))
403 #define FIO3CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x7E))
404 #define FIO4CLRU (*(reg16_t *)(FIO_BASE_ADDR + 0x9E))
407 /* System Control Block(SCB) modules include Memory Accelerator Module,
408 Phase Locked Loop, VPB divider, Power Control, External Interrupt,
409 Reset, and Code Security/Debugging */
410 #define SCB_BASE_ADDR 0xE01FC000
412 /* Memory Accelerator Module (MAM) */
413 #define MAMCR (*(reg32_t *)(SCB_BASE_ADDR + 0x000))
414 #define MAMTIM (*(reg32_t *)(SCB_BASE_ADDR + 0x004))
415 #define MEMMAP (*(reg32_t *)(SCB_BASE_ADDR + 0x040))
417 /* Phase Locked Loop (PLL) */
418 #define PLLCON (*(reg32_t *)(SCB_BASE_ADDR + 0x080))
419 #define PLLCFG (*(reg32_t *)(SCB_BASE_ADDR + 0x084))
420 #define PLLSTAT (*(reg32_t *)(SCB_BASE_ADDR + 0x088))
421 #define PLLFEED (*(reg32_t *)(SCB_BASE_ADDR + 0x08C))
424 #define PCON (*(reg32_t *)(SCB_BASE_ADDR + 0x0C0))
425 #define PCONP (*(reg32_t *)(SCB_BASE_ADDR + 0x0C4))
426 #define PCONP_PCI2C0 7
427 #define PCONP_PCI2C1 19
428 #define PCONP_PCI2C2 26
432 // #define APBDIV (*(reg32_t *)(SCB_BASE_ADDR + 0x100))
433 #define CCLKCFG (*(reg32_t *)(SCB_BASE_ADDR + 0x104))
434 #define USBCLKCFG (*(reg32_t *)(SCB_BASE_ADDR + 0x108))
435 #define CLKSRCSEL (*(reg32_t *)(SCB_BASE_ADDR + 0x10C))
436 #define PCLKSEL0 (*(reg32_t *)(SCB_BASE_ADDR + 0x1A8))
437 #define PCLKSEL1 (*(reg32_t *)(SCB_BASE_ADDR + 0x1AC))
439 #define CCLKCFG_OFF 0x104
440 #define USBCLKCFG_OFF 0x108
441 #define CLKSRCSEL_OFF 0x10C
442 #define PCLKSEL0_OFF 0x1A8
443 #define PCLKSEL1_OFF 0x1AC
446 /* External Interrupts */
447 #define EXTINT (*(reg32_t *)(SCB_BASE_ADDR + 0x140))
448 #define INTWAKE (*(reg32_t *)(SCB_BASE_ADDR + 0x144))
449 #define EXTMODE (*(reg32_t *)(SCB_BASE_ADDR + 0x148))
450 #define EXTPOLAR (*(reg32_t *)(SCB_BASE_ADDR + 0x14C))
452 /* Reset, reset source identification */
453 #define RSIR (*(reg32_t *)(SCB_BASE_ADDR + 0x180))
455 /* RSID, code security protection */
456 #define CSPR (*(reg32_t *)(SCB_BASE_ADDR + 0x184))
458 /* AHB configuration */
459 #define AHBCFG1 (*(reg32_t *)(SCB_BASE_ADDR + 0x188))
460 #define AHBCFG2 (*(reg32_t *)(SCB_BASE_ADDR + 0x18C))
462 /* System Controls and Status */
463 #define SCS (*(reg32_t *)(SCB_BASE_ADDR + 0x1A0))
465 /* MPMC(EMC) registers, note: all the external memory controller(EMC) registers
466 are for LPC24xx only. */
467 #define STATIC_MEM0_BASE 0x80000000
468 #define STATIC_MEM1_BASE 0x81000000
469 #define STATIC_MEM2_BASE 0x82000000
470 #define STATIC_MEM3_BASE 0x83000000
472 #define DYNAMIC_MEM0_BASE 0xA0000000
473 #define DYNAMIC_MEM1_BASE 0xB0000000
474 #define DYNAMIC_MEM2_BASE 0xC0000000
475 #define DYNAMIC_MEM3_BASE 0xD0000000
477 /* External Memory Controller (EMC) */
478 #define EMC_BASE_ADDR 0xFFE08000
479 #define EMC_CTRL (*(reg32_t *)(EMC_BASE_ADDR + 0x000))
480 #define EMC_STAT (*(reg32_t *)(EMC_BASE_ADDR + 0x004))
481 #define EMC_CONFIG (*(reg32_t *)(EMC_BASE_ADDR + 0x008))
483 /* Dynamic RAM access registers */
484 #define EMC_DYN_CTRL (*(reg32_t *)(EMC_BASE_ADDR + 0x020))
485 #define EMC_DYN_RFSH (*(reg32_t *)(EMC_BASE_ADDR + 0x024))
486 #define EMC_DYN_RD_CFG (*(reg32_t *)(EMC_BASE_ADDR + 0x028))
487 #define EMC_DYN_RP (*(reg32_t *)(EMC_BASE_ADDR + 0x030))
488 #define EMC_DYN_RAS (*(reg32_t *)(EMC_BASE_ADDR + 0x034))
489 #define EMC_DYN_SREX (*(reg32_t *)(EMC_BASE_ADDR + 0x038))
490 #define EMC_DYN_APR (*(reg32_t *)(EMC_BASE_ADDR + 0x03C))
491 #define EMC_DYN_DAL (*(reg32_t *)(EMC_BASE_ADDR + 0x040))
492 #define EMC_DYN_WR (*(reg32_t *)(EMC_BASE_ADDR + 0x044))
493 #define EMC_DYN_RC (*(reg32_t *)(EMC_BASE_ADDR + 0x048))
494 #define EMC_DYN_RFC (*(reg32_t *)(EMC_BASE_ADDR + 0x04C))
495 #define EMC_DYN_XSR (*(reg32_t *)(EMC_BASE_ADDR + 0x050))
496 #define EMC_DYN_RRD (*(reg32_t *)(EMC_BASE_ADDR + 0x054))
497 #define EMC_DYN_MRD (*(reg32_t *)(EMC_BASE_ADDR + 0x058))
499 #define EMC_DYN_CFG0 (*(reg32_t *)(EMC_BASE_ADDR + 0x100))
500 #define EMC_DYN_RASCAS0 (*(reg32_t *)(EMC_BASE_ADDR + 0x104))
501 #define EMC_DYN_CFG1 (*(reg32_t *)(EMC_BASE_ADDR + 0x140))
502 #define EMC_DYN_RASCAS1 (*(reg32_t *)(EMC_BASE_ADDR + 0x144))
503 #define EMC_DYN_CFG2 (*(reg32_t *)(EMC_BASE_ADDR + 0x160))
504 #define EMC_DYN_RASCAS2 (*(reg32_t *)(EMC_BASE_ADDR + 0x164))
505 #define EMC_DYN_CFG3 (*(reg32_t *)(EMC_BASE_ADDR + 0x180))
506 #define EMC_DYN_RASCAS3 (*(reg32_t *)(EMC_BASE_ADDR + 0x184))
508 /* static RAM access registers */
509 #define EMC_STA_CFG0 (*(reg32_t *)(EMC_BASE_ADDR + 0x200))
510 #define EMC_STA_WAITWEN0 (*(reg32_t *)(EMC_BASE_ADDR + 0x204))
511 #define EMC_STA_WAITOEN0 (*(reg32_t *)(EMC_BASE_ADDR + 0x208))
512 #define EMC_STA_WAITRD0 (*(reg32_t *)(EMC_BASE_ADDR + 0x20C))
513 #define EMC_STA_WAITPAGE0 (*(reg32_t *)(EMC_BASE_ADDR + 0x210))
514 #define EMC_STA_WAITWR0 (*(reg32_t *)(EMC_BASE_ADDR + 0x214))
515 #define EMC_STA_WAITTURN0 (*(reg32_t *)(EMC_BASE_ADDR + 0x218))
517 #define EMC_STA_CFG1 (*(reg32_t *)(EMC_BASE_ADDR + 0x220))
518 #define EMC_STA_WAITWEN1 (*(reg32_t *)(EMC_BASE_ADDR + 0x224))
519 #define EMC_STA_WAITOEN1 (*(reg32_t *)(EMC_BASE_ADDR + 0x228))
520 #define EMC_STA_WAITRD1 (*(reg32_t *)(EMC_BASE_ADDR + 0x22C))
521 #define EMC_STA_WAITPAGE1 (*(reg32_t *)(EMC_BASE_ADDR + 0x230))
522 #define EMC_STA_WAITWR1 (*(reg32_t *)(EMC_BASE_ADDR + 0x234))
523 #define EMC_STA_WAITTURN1 (*(reg32_t *)(EMC_BASE_ADDR + 0x238))
525 #define EMC_STA_CFG2 (*(reg32_t *)(EMC_BASE_ADDR + 0x240))
526 #define EMC_STA_WAITWEN2 (*(reg32_t *)(EMC_BASE_ADDR + 0x244))
527 #define EMC_STA_WAITOEN2 (*(reg32_t *)(EMC_BASE_ADDR + 0x248))
528 #define EMC_STA_WAITRD2 (*(reg32_t *)(EMC_BASE_ADDR + 0x24C))
529 #define EMC_STA_WAITPAGE2 (*(reg32_t *)(EMC_BASE_ADDR + 0x250))
530 #define EMC_STA_WAITWR2 (*(reg32_t *)(EMC_BASE_ADDR + 0x254))
531 #define EMC_STA_WAITTURN2 (*(reg32_t *)(EMC_BASE_ADDR + 0x258))
533 #define EMC_STA_CFG3 (*(reg32_t *)(EMC_BASE_ADDR + 0x260))
534 #define EMC_STA_WAITWEN3 (*(reg32_t *)(EMC_BASE_ADDR + 0x264))
535 #define EMC_STA_WAITOEN3 (*(reg32_t *)(EMC_BASE_ADDR + 0x268))
536 #define EMC_STA_WAITRD3 (*(reg32_t *)(EMC_BASE_ADDR + 0x26C))
537 #define EMC_STA_WAITPAGE3 (*(reg32_t *)(EMC_BASE_ADDR + 0x270))
538 #define EMC_STA_WAITWR3 (*(reg32_t *)(EMC_BASE_ADDR + 0x274))
539 #define EMC_STA_WAITTURN3 (*(reg32_t *)(EMC_BASE_ADDR + 0x278))
541 #define EMC_STA_EXT_WAIT (*(reg32_t *)(EMC_BASE_ADDR + 0x880))
545 #define TMR0_BASE_ADDR 0xE0004000
546 #define T0IR (*(reg32_t *)(TMR0_BASE_ADDR + 0x00))
547 #define T0TCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x04))
548 #define T0TC (*(reg32_t *)(TMR0_BASE_ADDR + 0x08))
549 #define T0PR (*(reg32_t *)(TMR0_BASE_ADDR + 0x0C))
550 #define T0PC (*(reg32_t *)(TMR0_BASE_ADDR + 0x10))
551 #define T0MCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x14))
552 #define T0MR0 (*(reg32_t *)(TMR0_BASE_ADDR + 0x18))
553 #define T0MR1 (*(reg32_t *)(TMR0_BASE_ADDR + 0x1C))
554 #define T0MR2 (*(reg32_t *)(TMR0_BASE_ADDR + 0x20))
555 #define T0MR3 (*(reg32_t *)(TMR0_BASE_ADDR + 0x24))
556 #define T0CCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x28))
557 #define T0CR0 (*(reg32_t *)(TMR0_BASE_ADDR + 0x2C))
558 #define T0CR1 (*(reg32_t *)(TMR0_BASE_ADDR + 0x30))
559 #define T0CR2 (*(reg32_t *)(TMR0_BASE_ADDR + 0x34))
560 #define T0CR3 (*(reg32_t *)(TMR0_BASE_ADDR + 0x38))
561 #define T0EMR (*(reg32_t *)(TMR0_BASE_ADDR + 0x3C))
562 #define T0CTCR (*(reg32_t *)(TMR0_BASE_ADDR + 0x70))
565 #define TMR1_BASE_ADDR 0xE0008000
566 #define T1IR (*(reg32_t *)(TMR1_BASE_ADDR + 0x00))
567 #define T1TCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x04))
568 #define T1TC (*(reg32_t *)(TMR1_BASE_ADDR + 0x08))
569 #define T1PR (*(reg32_t *)(TMR1_BASE_ADDR + 0x0C))
570 #define T1PC (*(reg32_t *)(TMR1_BASE_ADDR + 0x10))
571 #define T1MCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x14))
572 #define T1MR0 (*(reg32_t *)(TMR1_BASE_ADDR + 0x18))
573 #define T1MR1 (*(reg32_t *)(TMR1_BASE_ADDR + 0x1C))
574 #define T1MR2 (*(reg32_t *)(TMR1_BASE_ADDR + 0x20))
575 #define T1MR3 (*(reg32_t *)(TMR1_BASE_ADDR + 0x24))
576 #define T1CCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x28))
577 #define T1CR0 (*(reg32_t *)(TMR1_BASE_ADDR + 0x2C))
578 #define T1CR1 (*(reg32_t *)(TMR1_BASE_ADDR + 0x30))
579 #define T1CR2 (*(reg32_t *)(TMR1_BASE_ADDR + 0x34))
580 #define T1CR3 (*(reg32_t *)(TMR1_BASE_ADDR + 0x38))
581 #define T1EMR (*(reg32_t *)(TMR1_BASE_ADDR + 0x3C))
582 #define T1CTCR (*(reg32_t *)(TMR1_BASE_ADDR + 0x70))
585 #define TMR2_BASE_ADDR 0xE0070000
586 #define T2IR (*(reg32_t *)(TMR2_BASE_ADDR + 0x00))
587 #define T2TCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x04))
588 #define T2TC (*(reg32_t *)(TMR2_BASE_ADDR + 0x08))
589 #define T2PR (*(reg32_t *)(TMR2_BASE_ADDR + 0x0C))
590 #define T2PC (*(reg32_t *)(TMR2_BASE_ADDR + 0x10))
591 #define T2MCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x14))
592 #define T2MR0 (*(reg32_t *)(TMR2_BASE_ADDR + 0x18))
593 #define T2MR1 (*(reg32_t *)(TMR2_BASE_ADDR + 0x1C))
594 #define T2MR2 (*(reg32_t *)(TMR2_BASE_ADDR + 0x20))
595 #define T2MR3 (*(reg32_t *)(TMR2_BASE_ADDR + 0x24))
596 #define T2CCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x28))
597 #define T2CR0 (*(reg32_t *)(TMR2_BASE_ADDR + 0x2C))
598 #define T2CR1 (*(reg32_t *)(TMR2_BASE_ADDR + 0x30))
599 #define T2CR2 (*(reg32_t *)(TMR2_BASE_ADDR + 0x34))
600 #define T2CR3 (*(reg32_t *)(TMR2_BASE_ADDR + 0x38))
601 #define T2EMR (*(reg32_t *)(TMR2_BASE_ADDR + 0x3C))
602 #define T2CTCR (*(reg32_t *)(TMR2_BASE_ADDR + 0x70))
605 #define TMR3_BASE_ADDR 0xE0074000
606 #define T3IR (*(reg32_t *)(TMR3_BASE_ADDR + 0x00))
607 #define T3TCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x04))
608 #define T3TC (*(reg32_t *)(TMR3_BASE_ADDR + 0x08))
609 #define T3PR (*(reg32_t *)(TMR3_BASE_ADDR + 0x0C))
610 #define T3PC (*(reg32_t *)(TMR3_BASE_ADDR + 0x10))
611 #define T3MCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x14))
612 #define T3MR0 (*(reg32_t *)(TMR3_BASE_ADDR + 0x18))
613 #define T3MR1 (*(reg32_t *)(TMR3_BASE_ADDR + 0x1C))
614 #define T3MR2 (*(reg32_t *)(TMR3_BASE_ADDR + 0x20))
615 #define T3MR3 (*(reg32_t *)(TMR3_BASE_ADDR + 0x24))
616 #define T3CCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x28))
617 #define T3CR0 (*(reg32_t *)(TMR3_BASE_ADDR + 0x2C))
618 #define T3CR1 (*(reg32_t *)(TMR3_BASE_ADDR + 0x30))
619 #define T3CR2 (*(reg32_t *)(TMR3_BASE_ADDR + 0x34))
620 #define T3CR3 (*(reg32_t *)(TMR3_BASE_ADDR + 0x38))
621 #define T3EMR (*(reg32_t *)(TMR3_BASE_ADDR + 0x3C))
622 #define T3CTCR (*(reg32_t *)(TMR3_BASE_ADDR + 0x70))
625 /* Pulse Width Modulator (PWM) */
626 #define PWM0_BASE_ADDR 0xE0014000
627 #define PWM0IR (*(reg32_t *)(PWM0_BASE_ADDR + 0x00))
628 #define PWM0TCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x04))
629 #define PWM0TC (*(reg32_t *)(PWM0_BASE_ADDR + 0x08))
630 #define PWM0PR (*(reg32_t *)(PWM0_BASE_ADDR + 0x0C))
631 #define PWM0PC (*(reg32_t *)(PWM0_BASE_ADDR + 0x10))
632 #define PWM0MCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x14))
633 #define PWM0MR0 (*(reg32_t *)(PWM0_BASE_ADDR + 0x18))
634 #define PWM0MR1 (*(reg32_t *)(PWM0_BASE_ADDR + 0x1C))
635 #define PWM0MR2 (*(reg32_t *)(PWM0_BASE_ADDR + 0x20))
636 #define PWM0MR3 (*(reg32_t *)(PWM0_BASE_ADDR + 0x24))
637 #define PWM0CCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x28))
638 #define PWM0CR0 (*(reg32_t *)(PWM0_BASE_ADDR + 0x2C))
639 #define PWM0CR1 (*(reg32_t *)(PWM0_BASE_ADDR + 0x30))
640 #define PWM0CR2 (*(reg32_t *)(PWM0_BASE_ADDR + 0x34))
641 #define PWM0CR3 (*(reg32_t *)(PWM0_BASE_ADDR + 0x38))
642 #define PWM0EMR (*(reg32_t *)(PWM0_BASE_ADDR + 0x3C))
643 #define PWM0MR4 (*(reg32_t *)(PWM0_BASE_ADDR + 0x40))
644 #define PWM0MR5 (*(reg32_t *)(PWM0_BASE_ADDR + 0x44))
645 #define PWM0MR6 (*(reg32_t *)(PWM0_BASE_ADDR + 0x48))
646 #define PWM0PCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x4C))
647 #define PWM0LER (*(reg32_t *)(PWM0_BASE_ADDR + 0x50))
648 #define PWM0CTCR (*(reg32_t *)(PWM0_BASE_ADDR + 0x70))
650 #define PWM1_BASE_ADDR 0xE0018000
651 #define PWM1IR (*(reg32_t *)(PWM1_BASE_ADDR + 0x00))
652 #define PWM1TCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x04))
653 #define PWM1TC (*(reg32_t *)(PWM1_BASE_ADDR + 0x08))
654 #define PWM1PR (*(reg32_t *)(PWM1_BASE_ADDR + 0x0C))
655 #define PWM1PC (*(reg32_t *)(PWM1_BASE_ADDR + 0x10))
656 #define PWM1MCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x14))
657 #define PWM1MR0 (*(reg32_t *)(PWM1_BASE_ADDR + 0x18))
658 #define PWM1MR1 (*(reg32_t *)(PWM1_BASE_ADDR + 0x1C))
659 #define PWM1MR2 (*(reg32_t *)(PWM1_BASE_ADDR + 0x20))
660 #define PWM1MR3 (*(reg32_t *)(PWM1_BASE_ADDR + 0x24))
661 #define PWM1CCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x28))
662 #define PWM1CR0 (*(reg32_t *)(PWM1_BASE_ADDR + 0x2C))
663 #define PWM1CR1 (*(reg32_t *)(PWM1_BASE_ADDR + 0x30))
664 #define PWM1CR2 (*(reg32_t *)(PWM1_BASE_ADDR + 0x34))
665 #define PWM1CR3 (*(reg32_t *)(PWM1_BASE_ADDR + 0x38))
666 #define PWM1EMR (*(reg32_t *)(PWM1_BASE_ADDR + 0x3C))
667 #define PWM1MR4 (*(reg32_t *)(PWM1_BASE_ADDR + 0x40))
668 #define PWM1MR5 (*(reg32_t *)(PWM1_BASE_ADDR + 0x44))
669 #define PWM1MR6 (*(reg32_t *)(PWM1_BASE_ADDR + 0x48))
670 #define PWM1PCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x4C))
671 #define PWM1LER (*(reg32_t *)(PWM1_BASE_ADDR + 0x50))
672 #define PWM1CTCR (*(reg32_t *)(PWM1_BASE_ADDR + 0x70))
675 /* Universal Asynchronous Receiver Transmitter 0 (UART0) */
676 #define UART0_BASE_ADDR 0xE000C000
677 #define U0RBR (*(reg32_t *)(UART0_BASE_ADDR + 0x00))
678 #define U0THR (*(reg32_t *)(UART0_BASE_ADDR + 0x00))
679 #define U0DLL (*(reg32_t *)(UART0_BASE_ADDR + 0x00))
680 #define U0DLM (*(reg32_t *)(UART0_BASE_ADDR + 0x04))
681 #define U0IER (*(reg32_t *)(UART0_BASE_ADDR + 0x04))
682 #define U0IIR (*(reg32_t *)(UART0_BASE_ADDR + 0x08))
683 #define U0FCR (*(reg32_t *)(UART0_BASE_ADDR + 0x08))
684 #define U0LCR (*(reg32_t *)(UART0_BASE_ADDR + 0x0C))
685 #define U0LSR (*(reg32_t *)(UART0_BASE_ADDR + 0x14))
686 #define U0SCR (*(reg32_t *)(UART0_BASE_ADDR + 0x1C))
687 #define U0ACR (*(reg32_t *)(UART0_BASE_ADDR + 0x20))
688 #define U0ICR (*(reg32_t *)(UART0_BASE_ADDR + 0x24))
689 #define U0FDR (*(reg32_t *)(UART0_BASE_ADDR + 0x28))
690 #define U0TER (*(reg32_t *)(UART0_BASE_ADDR + 0x30))
692 /* Universal Asynchronous Receiver Transmitter 1 (UART1) */
693 #define UART1_BASE_ADDR 0xE0010000
694 #define U1RBR (*(reg32_t *)(UART1_BASE_ADDR + 0x00))
695 #define U1THR (*(reg32_t *)(UART1_BASE_ADDR + 0x00))
696 #define U1DLL (*(reg32_t *)(UART1_BASE_ADDR + 0x00))
697 #define U1DLM (*(reg32_t *)(UART1_BASE_ADDR + 0x04))
698 #define U1IER (*(reg32_t *)(UART1_BASE_ADDR + 0x04))
699 #define U1IIR (*(reg32_t *)(UART1_BASE_ADDR + 0x08))
700 #define U1FCR (*(reg32_t *)(UART1_BASE_ADDR + 0x08))
701 #define U1LCR (*(reg32_t *)(UART1_BASE_ADDR + 0x0C))
702 #define U1MCR (*(reg32_t *)(UART1_BASE_ADDR + 0x10))
703 #define U1LSR (*(reg32_t *)(UART1_BASE_ADDR + 0x14))
704 #define U1MSR (*(reg32_t *)(UART1_BASE_ADDR + 0x18))
705 #define U1SCR (*(reg32_t *)(UART1_BASE_ADDR + 0x1C))
706 #define U1ACR (*(reg32_t *)(UART1_BASE_ADDR + 0x20))
707 #define U1FDR (*(reg32_t *)(UART1_BASE_ADDR + 0x28))
708 #define U1TER (*(reg32_t *)(UART1_BASE_ADDR + 0x30))
710 /* Universal Asynchronous Receiver Transmitter 2 (UART2) */
711 #define UART2_BASE_ADDR 0xE0078000
712 #define U2RBR (*(reg32_t *)(UART2_BASE_ADDR + 0x00))
713 #define U2THR (*(reg32_t *)(UART2_BASE_ADDR + 0x00))
714 #define U2DLL (*(reg32_t *)(UART2_BASE_ADDR + 0x00))
715 #define U2DLM (*(reg32_t *)(UART2_BASE_ADDR + 0x04))
716 #define U2IER (*(reg32_t *)(UART2_BASE_ADDR + 0x04))
717 #define U2IIR (*(reg32_t *)(UART2_BASE_ADDR + 0x08))
718 #define U2FCR (*(reg32_t *)(UART2_BASE_ADDR + 0x08))
719 #define U2LCR (*(reg32_t *)(UART2_BASE_ADDR + 0x0C))
720 #define U2LSR (*(reg32_t *)(UART2_BASE_ADDR + 0x14))
721 #define U2SCR (*(reg32_t *)(UART2_BASE_ADDR + 0x1C))
722 #define U2ACR (*(reg32_t *)(UART2_BASE_ADDR + 0x20))
723 #define U2ICR (*(reg32_t *)(UART2_BASE_ADDR + 0x24))
724 #define U2FDR (*(reg32_t *)(UART2_BASE_ADDR + 0x28))
725 #define U2TER (*(reg32_t *)(UART2_BASE_ADDR + 0x30))
727 /* Universal Asynchronous Receiver Transmitter 3 (UART3) */
728 #define UART3_BASE_ADDR 0xE007C000
729 #define U3RBR (*(reg32_t *)(UART3_BASE_ADDR + 0x00))
730 #define U3THR (*(reg32_t *)(UART3_BASE_ADDR + 0x00))
731 #define U3DLL (*(reg32_t *)(UART3_BASE_ADDR + 0x00))
732 #define U3DLM (*(reg32_t *)(UART3_BASE_ADDR + 0x04))
733 #define U3IER (*(reg32_t *)(UART3_BASE_ADDR + 0x04))
734 #define U3IIR (*(reg32_t *)(UART3_BASE_ADDR + 0x08))
735 #define U3FCR (*(reg32_t *)(UART3_BASE_ADDR + 0x08))
736 #define U3LCR (*(reg32_t *)(UART3_BASE_ADDR + 0x0C))
737 #define U3LSR (*(reg32_t *)(UART3_BASE_ADDR + 0x14))
738 #define U3SCR (*(reg32_t *)(UART3_BASE_ADDR + 0x1C))
739 #define U3ACR (*(reg32_t *)(UART3_BASE_ADDR + 0x20))
740 #define U3ICR (*(reg32_t *)(UART3_BASE_ADDR + 0x24))
741 #define U3FDR (*(reg32_t *)(UART3_BASE_ADDR + 0x28))
742 #define U3TER (*(reg32_t *)(UART3_BASE_ADDR + 0x30))
744 /* I2C Interface 0 */
745 #define I2C0_BASE_ADDR 0xE001C000
746 #define I20CONSET (*(reg32_t *)(I2C0_BASE_ADDR + 0x00))
747 #define I20STAT (*(reg32_t *)(I2C0_BASE_ADDR + 0x04))
748 #define I20DAT (*(reg32_t *)(I2C0_BASE_ADDR + 0x08))
749 #define I20ADR (*(reg32_t *)(I2C0_BASE_ADDR + 0x0C))
750 #define I20SCLH (*(reg32_t *)(I2C0_BASE_ADDR + 0x10))
751 #define I20SCLL (*(reg32_t *)(I2C0_BASE_ADDR + 0x14))
752 #define I20CONCLR (*(reg32_t *)(I2C0_BASE_ADDR + 0x18))
754 /* I2C Interface 1 */
755 #define I2C1_BASE_ADDR 0xE005C000
756 #define I21CONSET (*(reg32_t *)(I2C1_BASE_ADDR + 0x00))
757 #define I21STAT (*(reg32_t *)(I2C1_BASE_ADDR + 0x04))
758 #define I21DAT (*(reg32_t *)(I2C1_BASE_ADDR + 0x08))
759 #define I21ADR (*(reg32_t *)(I2C1_BASE_ADDR + 0x0C))
760 #define I21SCLH (*(reg32_t *)(I2C1_BASE_ADDR + 0x10))
761 #define I21SCLL (*(reg32_t *)(I2C1_BASE_ADDR + 0x14))
762 #define I21CONCLR (*(reg32_t *)(I2C1_BASE_ADDR + 0x18))
764 /* I2C Interface 2 */
765 #define I2C2_BASE_ADDR 0xE0080000
766 #define I22CONSET (*(reg32_t *)(I2C2_BASE_ADDR + 0x00))
767 #define I22STAT (*(reg32_t *)(I2C2_BASE_ADDR + 0x04))
768 #define I22DAT (*(reg32_t *)(I2C2_BASE_ADDR + 0x08))
769 #define I22ADR (*(reg32_t *)(I2C2_BASE_ADDR + 0x0C))
770 #define I22SCLH (*(reg32_t *)(I2C2_BASE_ADDR + 0x10))
771 #define I22SCLL (*(reg32_t *)(I2C2_BASE_ADDR + 0x14))
772 #define I22CONCLR (*(reg32_t *)(I2C2_BASE_ADDR + 0x18))
775 #define I2C_CONSET_OFF 0x00
776 #define I2C_STAT_OFF 0x04
777 #define I2C_DAT_OFF 0x08
778 #define I2C_ADR_OFF 0x0C
779 #define I2C_SCLH_OFF 0x10
780 #define I2C_SCLL_OFF 0x14
781 #define I2C_CONCLR_OFF 0x18
783 /* I2C register definition Clear */
784 #define I2CON_I2ENC 6 // I2C interface Disable bit
785 #define I2CON_STAC 5 // START flag Clear bit
786 #define I2CON_SIC 3 // I2C interrupt Clear bit
787 #define I2CON_AAC 2 // Assert acknowledge Clear bit
789 /* I2C register definition Set */
790 #define I2CON_I2EN 6 // I2C interface enable
791 #define I2CON_STA 5 // START flag Clear bit
792 #define I2CON_STO 4 // STOP flag Clear bit
793 #define I2CON_SI 3 // I2C interrupt Clear bit
794 #define I2CON_AA 2 // Assert acknowledge Clear bit
796 /* I2C Status codes */
797 #define I2C_STAT_ERROR 0x00
798 #define I2C_STAT_UNKNOW 0xF8
799 #define I2C_STAT_SEND 0x08
800 #define I2C_STAT_RESEND 0x10
801 #define I2C_STAT_SLAW_ACK 0x18
802 #define I2C_STAT_SLAW_NACK 0x20
803 #define I2C_STAT_SLAR_ACK 0x40
804 #define I2C_STAT_SLAR_NACK 0x48
805 #define I2C_STAT_DATA_ACK 0x28
806 #define I2C_STAT_DATA_NACK 0x30
807 #define I2C_STAT_RDATA_ACK 0x50
808 #define I2C_STAT_RDATA_NACK 0x58
809 #define I2C_STAT_ARB_LOST 0x38
811 #define I2C0_PCLK_MASK 0xC000
812 #define I2C0_PCLK_DIV8 0xC000
813 #define I2C0_PCLK_DIV4 0x4000
814 #define I2C1_PCLK_MASK 0x00C0
815 #define I2C1_PCLK_DIV8 0x00C0
816 #define I2C1_PCLK_DIV4 0x0040
817 #define I2C2_PCLK_MASK 0x300000
818 #define I2C2_PCLK_DIV8 0x300000
819 #define I2C2_PCLK_DIV4 0x100000
821 /* I2C pins defines */
822 #define I2C0_PINSEL_MASK 0x3C00000
823 #define I2C0_PINSEL 0x1400000
824 #define I2C1_PINSEL_MASK 0x000000F
825 #define I2C1_PINSEL 0x000000F
826 #define I2C2_PINSEL_MASK 0x0F00000
827 #define I2C2_PINSEL 0x0A00000
829 /* SPI0 (Serial Peripheral Interface 0) */
830 #define SPI0_BASE_ADDR 0xE0020000
831 #define S0SPCR (*(reg32_t *)(SPI0_BASE_ADDR + 0x00))
832 #define S0SPSR (*(reg32_t *)(SPI0_BASE_ADDR + 0x04))
833 #define S0SPDR (*(reg32_t *)(SPI0_BASE_ADDR + 0x08))
834 #define S0SPCCR (*(reg32_t *)(SPI0_BASE_ADDR + 0x0C))
835 #define S0SPINT (*(reg32_t *)(SPI0_BASE_ADDR + 0x1C))
837 /* SSP0 Controller */
838 #define SSP0_BASE_ADDR 0xE0068000
839 #define SSP0CR0 (*(reg32_t *)(SSP0_BASE_ADDR + 0x00))
840 #define SSP0CR1 (*(reg32_t *)(SSP0_BASE_ADDR + 0x04))
841 #define SSP0DR (*(reg32_t *)(SSP0_BASE_ADDR + 0x08))
842 #define SSP0SR (*(reg32_t *)(SSP0_BASE_ADDR + 0x0C))
843 #define SSP0CPSR (*(reg32_t *)(SSP0_BASE_ADDR + 0x10))
844 #define SSP0IMSC (*(reg32_t *)(SSP0_BASE_ADDR + 0x14))
845 #define SSP0RIS (*(reg32_t *)(SSP0_BASE_ADDR + 0x18))
846 #define SSP0MIS (*(reg32_t *)(SSP0_BASE_ADDR + 0x1C))
847 #define SSP0ICR (*(reg32_t *)(SSP0_BASE_ADDR + 0x20))
848 #define SSP0DMACR (*(reg32_t *)(SSP0_BASE_ADDR + 0x24))
850 /* SSP1 Controller */
851 #define SSP1_BASE_ADDR 0xE0030000
852 #define SSP1CR0 (*(reg32_t *)(SSP1_BASE_ADDR + 0x00))
853 #define SSP1CR1 (*(reg32_t *)(SSP1_BASE_ADDR + 0x04))
854 #define SSP1DR (*(reg32_t *)(SSP1_BASE_ADDR + 0x08))
855 #define SSP1SR (*(reg32_t *)(SSP1_BASE_ADDR + 0x0C))
856 #define SSP1CPSR (*(reg32_t *)(SSP1_BASE_ADDR + 0x10))
857 #define SSP1IMSC (*(reg32_t *)(SSP1_BASE_ADDR + 0x14))
858 #define SSP1RIS (*(reg32_t *)(SSP1_BASE_ADDR + 0x18))
859 #define SSP1MIS (*(reg32_t *)(SSP1_BASE_ADDR + 0x1C))
860 #define SSP1ICR (*(reg32_t *)(SSP1_BASE_ADDR + 0x20))
861 #define SSP1DMACR (*(reg32_t *)(SSP1_BASE_ADDR + 0x24))
864 /* Real Time Clock */
865 #define RTC_BASE_ADDR 0xE0024000
866 #define RTC_ILR (*(reg32_t *)(RTC_BASE_ADDR + 0x00))
867 #define RTC_CTC (*(reg32_t *)(RTC_BASE_ADDR + 0x04))
868 #define RTC_CCR (*(reg32_t *)(RTC_BASE_ADDR + 0x08))
869 #define RTC_CIIR (*(reg32_t *)(RTC_BASE_ADDR + 0x0C))
870 #define RTC_AMR (*(reg32_t *)(RTC_BASE_ADDR + 0x10))
871 #define RTC_CTIME0 (*(reg32_t *)(RTC_BASE_ADDR + 0x14))
872 #define RTC_CTIME1 (*(reg32_t *)(RTC_BASE_ADDR + 0x18))
873 #define RTC_CTIME2 (*(reg32_t *)(RTC_BASE_ADDR + 0x1C))
874 #define RTC_SEC (*(reg32_t *)(RTC_BASE_ADDR + 0x20))
875 #define RTC_MIN (*(reg32_t *)(RTC_BASE_ADDR + 0x24))
876 #define RTC_HOUR (*(reg32_t *)(RTC_BASE_ADDR + 0x28))
877 #define RTC_DOM (*(reg32_t *)(RTC_BASE_ADDR + 0x2C))
878 #define RTC_DOW (*(reg32_t *)(RTC_BASE_ADDR + 0x30))
879 #define RTC_DOY (*(reg32_t *)(RTC_BASE_ADDR + 0x34))
880 #define RTC_MONTH (*(reg32_t *)(RTC_BASE_ADDR + 0x38))
881 #define RTC_YEAR (*(reg32_t *)(RTC_BASE_ADDR + 0x3C))
882 #define RTC_CISS (*(reg32_t *)(RTC_BASE_ADDR + 0x40))
883 #define RTC_ALSEC (*(reg32_t *)(RTC_BASE_ADDR + 0x60))
884 #define RTC_ALMIN (*(reg32_t *)(RTC_BASE_ADDR + 0x64))
885 #define RTC_ALHOUR (*(reg32_t *)(RTC_BASE_ADDR + 0x68))
886 #define RTC_ALDOM (*(reg32_t *)(RTC_BASE_ADDR + 0x6C))
887 #define RTC_ALDOW (*(reg32_t *)(RTC_BASE_ADDR + 0x70))
888 #define RTC_ALDOY (*(reg32_t *)(RTC_BASE_ADDR + 0x74))
889 #define RTC_ALMON (*(reg32_t *)(RTC_BASE_ADDR + 0x78))
890 #define RTC_ALYEAR (*(reg32_t *)(RTC_BASE_ADDR + 0x7C))
891 #define RTC_PREINT (*(reg32_t *)(RTC_BASE_ADDR + 0x80))
892 #define RTC_PREFRAC (*(reg32_t *)(RTC_BASE_ADDR + 0x84))
895 /* A/D Converter 0 (AD0) */
896 #define AD0_BASE_ADDR 0xE0034000
897 #define AD0CR (*(reg32_t *)(AD0_BASE_ADDR + 0x00))
898 #define AD0GDR (*(reg32_t *)(AD0_BASE_ADDR + 0x04))
899 #define AD0INTEN (*(reg32_t *)(AD0_BASE_ADDR + 0x0C))
900 #define AD0DR0 (*(reg32_t *)(AD0_BASE_ADDR + 0x10))
901 #define AD0DR1 (*(reg32_t *)(AD0_BASE_ADDR + 0x14))
902 #define AD0DR2 (*(reg32_t *)(AD0_BASE_ADDR + 0x18))
903 #define AD0DR3 (*(reg32_t *)(AD0_BASE_ADDR + 0x1C))
904 #define AD0DR4 (*(reg32_t *)(AD0_BASE_ADDR + 0x20))
905 #define AD0DR5 (*(reg32_t *)(AD0_BASE_ADDR + 0x24))
906 #define AD0DR6 (*(reg32_t *)(AD0_BASE_ADDR + 0x28))
907 #define AD0DR7 (*(reg32_t *)(AD0_BASE_ADDR + 0x2C))
908 #define AD0STAT (*(reg32_t *)(AD0_BASE_ADDR + 0x30))
912 #define DAC_BASE_ADDR 0xE006C000
913 #define DACR (*(reg32_t *)(DAC_BASE_ADDR + 0x00))
917 #define WDG_BASE_ADDR 0xE0000000
918 #define WDMOD (*(reg32_t *)(WDG_BASE_ADDR + 0x00))
919 #define WDTC (*(reg32_t *)(WDG_BASE_ADDR + 0x04))
920 #define WDFEED (*(reg32_t *)(WDG_BASE_ADDR + 0x08))
921 #define WDTV (*(reg32_t *)(WDG_BASE_ADDR + 0x0C))
922 #define WDCLKSEL (*(reg32_t *)(WDG_BASE_ADDR + 0x10))
924 /* CAN CONTROLLERS AND ACCEPTANCE FILTER */
925 #define CAN_ACCEPT_BASE_ADDR 0xE003C000
926 #define CAN_AFMR (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x00))
927 #define CAN_SFF_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x04))
928 #define CAN_SFF_GRP_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x08))
929 #define CAN_EFF_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x0C))
930 #define CAN_EFF_GRP_SA (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x10))
931 #define CAN_EOT (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x14))
932 #define CAN_LUT_ERR_ADR (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x18))
933 #define CAN_LUT_ERR (*(reg32_t *)(CAN_ACCEPT_BASE_ADDR + 0x1C))
935 #define CAN_CENTRAL_BASE_ADDR 0xE0040000
936 #define CAN_TX_SR (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x00))
937 #define CAN_RX_SR (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x04))
938 #define CAN_MSR (*(reg32_t *)(CAN_CENTRAL_BASE_ADDR + 0x08))
940 #define CAN1_BASE_ADDR 0xE0044000
941 #define CAN1MOD (*(reg32_t *)(CAN1_BASE_ADDR + 0x00))
942 #define CAN1CMR (*(reg32_t *)(CAN1_BASE_ADDR + 0x04))
943 #define CAN1GSR (*(reg32_t *)(CAN1_BASE_ADDR + 0x08))
944 #define CAN1ICR (*(reg32_t *)(CAN1_BASE_ADDR + 0x0C))
945 #define CAN1IER (*(reg32_t *)(CAN1_BASE_ADDR + 0x10))
946 #define CAN1BTR (*(reg32_t *)(CAN1_BASE_ADDR + 0x14))
947 #define CAN1EWL (*(reg32_t *)(CAN1_BASE_ADDR + 0x18))
948 #define CAN1SR (*(reg32_t *)(CAN1_BASE_ADDR + 0x1C))
949 #define CAN1RFS (*(reg32_t *)(CAN1_BASE_ADDR + 0x20))
950 #define CAN1RID (*(reg32_t *)(CAN1_BASE_ADDR + 0x24))
951 #define CAN1RDA (*(reg32_t *)(CAN1_BASE_ADDR + 0x28))
952 #define CAN1RDB (*(reg32_t *)(CAN1_BASE_ADDR + 0x2C))
954 #define CAN1TFI1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x30))
955 #define CAN1TID1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x34))
956 #define CAN1TDA1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x38))
957 #define CAN1TDB1 (*(reg32_t *)(CAN1_BASE_ADDR + 0x3C))
958 #define CAN1TFI2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x40))
959 #define CAN1TID2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x44))
960 #define CAN1TDA2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x48))
961 #define CAN1TDB2 (*(reg32_t *)(CAN1_BASE_ADDR + 0x4C))
962 #define CAN1TFI3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x50))
963 #define CAN1TID3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x54))
964 #define CAN1TDA3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x58))
965 #define CAN1TDB3 (*(reg32_t *)(CAN1_BASE_ADDR + 0x5C))
967 #define CAN2_BASE_ADDR 0xE0048000
968 #define CAN2MOD (*(reg32_t *)(CAN2_BASE_ADDR + 0x00))
969 #define CAN2CMR (*(reg32_t *)(CAN2_BASE_ADDR + 0x04))
970 #define CAN2GSR (*(reg32_t *)(CAN2_BASE_ADDR + 0x08))
971 #define CAN2ICR (*(reg32_t *)(CAN2_BASE_ADDR + 0x0C))
972 #define CAN2IER (*(reg32_t *)(CAN2_BASE_ADDR + 0x10))
973 #define CAN2BTR (*(reg32_t *)(CAN2_BASE_ADDR + 0x14))
974 #define CAN2EWL (*(reg32_t *)(CAN2_BASE_ADDR + 0x18))
975 #define CAN2SR (*(reg32_t *)(CAN2_BASE_ADDR + 0x1C))
976 #define CAN2RFS (*(reg32_t *)(CAN2_BASE_ADDR + 0x20))
977 #define CAN2RID (*(reg32_t *)(CAN2_BASE_ADDR + 0x24))
978 #define CAN2RDA (*(reg32_t *)(CAN2_BASE_ADDR + 0x28))
979 #define CAN2RDB (*(reg32_t *)(CAN2_BASE_ADDR + 0x2C))
981 #define CAN2TFI1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x30))
982 #define CAN2TID1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x34))
983 #define CAN2TDA1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x38))
984 #define CAN2TDB1 (*(reg32_t *)(CAN2_BASE_ADDR + 0x3C))
985 #define CAN2TFI2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x40))
986 #define CAN2TID2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x44))
987 #define CAN2TDA2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x48))
988 #define CAN2TDB2 (*(reg32_t *)(CAN2_BASE_ADDR + 0x4C))
989 #define CAN2TFI3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x50))
990 #define CAN2TID3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x54))
991 #define CAN2TDA3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x58))
992 #define CAN2TDB3 (*(reg32_t *)(CAN2_BASE_ADDR + 0x5C))
995 /* MultiMedia Card Interface(MCI) Controller */
996 #define MCI_BASE_ADDR 0xE008C000
997 #define MCI_POWER (*(reg32_t *)(MCI_BASE_ADDR + 0x00))
998 #define MCI_CLOCK (*(reg32_t *)(MCI_BASE_ADDR + 0x04))
999 #define MCI_ARGUMENT (*(reg32_t *)(MCI_BASE_ADDR + 0x08))
1000 #define MCI_COMMAND (*(reg32_t *)(MCI_BASE_ADDR + 0x0C))
1001 #define MCI_RESP_CMD (*(reg32_t *)(MCI_BASE_ADDR + 0x10))
1002 #define MCI_RESP0 (*(reg32_t *)(MCI_BASE_ADDR + 0x14))
1003 #define MCI_RESP1 (*(reg32_t *)(MCI_BASE_ADDR + 0x18))
1004 #define MCI_RESP2 (*(reg32_t *)(MCI_BASE_ADDR + 0x1C))
1005 #define MCI_RESP3 (*(reg32_t *)(MCI_BASE_ADDR + 0x20))
1006 #define MCI_DATA_TMR (*(reg32_t *)(MCI_BASE_ADDR + 0x24))
1007 #define MCI_DATA_LEN (*(reg32_t *)(MCI_BASE_ADDR + 0x28))
1008 #define MCI_DATA_CTRL (*(reg32_t *)(MCI_BASE_ADDR + 0x2C))
1009 #define MCI_DATA_CNT (*(reg32_t *)(MCI_BASE_ADDR + 0x30))
1010 #define MCI_STATUS (*(reg32_t *)(MCI_BASE_ADDR + 0x34))
1011 #define MCI_CLEAR (*(reg32_t *)(MCI_BASE_ADDR + 0x38))
1012 #define MCI_MASK0 (*(reg32_t *)(MCI_BASE_ADDR + 0x3C))
1013 #define MCI_MASK1 (*(reg32_t *)(MCI_BASE_ADDR + 0x40))
1014 #define MCI_FIFO_CNT (*(reg32_t *)(MCI_BASE_ADDR + 0x48))
1015 #define MCI_FIFO (*(reg32_t *)(MCI_BASE_ADDR + 0x80))
1018 /* I2S Interface Controller (I2S) */
1019 #define I2S_BASE_ADDR 0xE0088000
1020 #define I2S_DAO (*(reg32_t *)(I2S_BASE_ADDR + 0x00))
1021 #define I2S_DAI (*(reg32_t *)(I2S_BASE_ADDR + 0x04))
1022 #define I2S_TX_FIFO (*(reg32_t *)(I2S_BASE_ADDR + 0x08))
1023 #define I2S_RX_FIFO (*(reg32_t *)(I2S_BASE_ADDR + 0x0C))
1024 #define I2S_STATE (*(reg32_t *)(I2S_BASE_ADDR + 0x10))
1025 #define I2S_DMA1 (*(reg32_t *)(I2S_BASE_ADDR + 0x14))
1026 #define I2S_DMA2 (*(reg32_t *)(I2S_BASE_ADDR + 0x18))
1027 #define I2S_IRQ (*(reg32_t *)(I2S_BASE_ADDR + 0x1C))
1028 #define I2S_TXRATE (*(reg32_t *)(I2S_BASE_ADDR + 0x20))
1029 #define I2S_RXRATE (*(reg32_t *)(I2S_BASE_ADDR + 0x24))
1032 /* General-purpose DMA Controller */
1033 #define DMA_BASE_ADDR 0xFFE04000
1034 #define GPDMA_INT_STAT (*(reg32_t *)(DMA_BASE_ADDR + 0x000))
1035 #define GPDMA_INT_TCSTAT (*(reg32_t *)(DMA_BASE_ADDR + 0x004))
1036 #define GPDMA_INT_TCCLR (*(reg32_t *)(DMA_BASE_ADDR + 0x008))
1037 #define GPDMA_INT_ERR_STAT (*(reg32_t *)(DMA_BASE_ADDR + 0x00C))
1038 #define GPDMA_INT_ERR_CLR (*(reg32_t *)(DMA_BASE_ADDR + 0x010))
1039 #define GPDMA_RAW_INT_TCSTAT (*(reg32_t *)(DMA_BASE_ADDR + 0x014))
1040 #define GPDMA_RAW_INT_ERR_STAT (*(reg32_t *)(DMA_BASE_ADDR + 0x018))
1041 #define GPDMA_ENABLED_CHNS (*(reg32_t *)(DMA_BASE_ADDR + 0x01C))
1042 #define GPDMA_SOFT_BREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x020))
1043 #define GPDMA_SOFT_SREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x024))
1044 #define GPDMA_SOFT_LBREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x028))
1045 #define GPDMA_SOFT_LSREQ (*(reg32_t *)(DMA_BASE_ADDR + 0x02C))
1046 #define GPDMA_CONFIG (*(reg32_t *)(DMA_BASE_ADDR + 0x030))
1047 #define GPDMA_SYNC (*(reg32_t *)(DMA_BASE_ADDR + 0x034))
1049 /* DMA channel 0 registers */
1050 #define GPDMA_CH0_SRC (*(reg32_t *)(DMA_BASE_ADDR + 0x100))
1051 #define GPDMA_CH0_DEST (*(reg32_t *)(DMA_BASE_ADDR + 0x104))
1052 #define GPDMA_CH0_LLI (*(reg32_t *)(DMA_BASE_ADDR + 0x108))
1053 #define GPDMA_CH0_CTRL (*(reg32_t *)(DMA_BASE_ADDR + 0x10C))
1054 #define GPDMA_CH0_CFG (*(reg32_t *)(DMA_BASE_ADDR + 0x110))
1056 /* DMA channel 1 registers */
1057 #define GPDMA_CH1_SRC (*(reg32_t *)(DMA_BASE_ADDR + 0x120))
1058 #define GPDMA_CH1_DEST (*(reg32_t *)(DMA_BASE_ADDR + 0x124))
1059 #define GPDMA_CH1_LLI (*(reg32_t *)(DMA_BASE_ADDR + 0x128))
1060 #define GPDMA_CH1_CTRL (*(reg32_t *)(DMA_BASE_ADDR + 0x12C))
1061 #define GPDMA_CH1_CFG (*(reg32_t *)(DMA_BASE_ADDR + 0x130))
1064 /* USB Controller */
1065 #define USB_INT_BASE_ADDR 0xE01FC1C0
1066 #define USB_BASE_ADDR 0xFFE0C200 /* USB Base Address */
1068 #define USB_INT_STAT (*(reg32_t *)(USB_INT_BASE_ADDR + 0x00))
1070 /* USB Device Interrupt Registers */
1071 #define DEV_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x00))
1072 #define DEV_INT_EN (*(reg32_t *)(USB_BASE_ADDR + 0x04))
1073 #define DEV_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0x08))
1074 #define DEV_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0x0C))
1075 #define DEV_INT_PRIO (*(reg32_t *)(USB_BASE_ADDR + 0x2C))
1077 /* USB Device Endpoint Interrupt Registers */
1078 #define EP_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x30))
1079 #define EP_INT_EN (*(reg32_t *)(USB_BASE_ADDR + 0x34))
1080 #define EP_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0x38))
1081 #define EP_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0x3C))
1082 #define EP_INT_PRIO (*(reg32_t *)(USB_BASE_ADDR + 0x40))
1084 /* USB Device Endpoint Realization Registers */
1085 #define REALIZE_EP (*(reg32_t *)(USB_BASE_ADDR + 0x44))
1086 #define EP_INDEX (*(reg32_t *)(USB_BASE_ADDR + 0x48))
1087 #define MAXPACKET_SIZE (*(reg32_t *)(USB_BASE_ADDR + 0x4C))
1089 /* USB Device Command Reagisters */
1090 #define CMD_CODE (*(reg32_t *)(USB_BASE_ADDR + 0x10))
1091 #define CMD_DATA (*(reg32_t *)(USB_BASE_ADDR + 0x14))
1093 /* USB Device Data Transfer Registers */
1094 #define RX_DATA (*(reg32_t *)(USB_BASE_ADDR + 0x18))
1095 #define TX_DATA (*(reg32_t *)(USB_BASE_ADDR + 0x1C))
1096 #define RX_PLENGTH (*(reg32_t *)(USB_BASE_ADDR + 0x20))
1097 #define TX_PLENGTH (*(reg32_t *)(USB_BASE_ADDR + 0x24))
1098 #define USB_CTRL (*(reg32_t *)(USB_BASE_ADDR + 0x28))
1100 /* USB Device DMA Registers */
1101 #define DMA_REQ_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x50))
1102 #define DMA_REQ_CLR (*(reg32_t *)(USB_BASE_ADDR + 0x54))
1103 #define DMA_REQ_SET (*(reg32_t *)(USB_BASE_ADDR + 0x58))
1104 #define UDCA_HEAD (*(reg32_t *)(USB_BASE_ADDR + 0x80))
1105 #define EP_DMA_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x84))
1106 #define EP_DMA_EN (*(reg32_t *)(USB_BASE_ADDR + 0x88))
1107 #define EP_DMA_DIS (*(reg32_t *)(USB_BASE_ADDR + 0x8C))
1108 #define DMA_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0x90))
1109 #define DMA_INT_EN (*(reg32_t *)(USB_BASE_ADDR + 0x94))
1110 #define EOT_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0xA0))
1111 #define EOT_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0xA4))
1112 #define EOT_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0xA8))
1113 #define NDD_REQ_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0xAC))
1114 #define NDD_REQ_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0xB0))
1115 #define NDD_REQ_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0xB4))
1116 #define SYS_ERR_INT_STAT (*(reg32_t *)(USB_BASE_ADDR + 0xB8))
1117 #define SYS_ERR_INT_CLR (*(reg32_t *)(USB_BASE_ADDR + 0xBC))
1118 #define SYS_ERR_INT_SET (*(reg32_t *)(USB_BASE_ADDR + 0xC0))
1120 /* USB Host and OTG registers are for LPC24xx only */
1121 /* USB Host Controller */
1122 #define USBHC_BASE_ADDR 0xFFE0C000
1123 #define HC_REVISION (*(reg32_t *)(USBHC_BASE_ADDR + 0x00))
1124 #define HC_CONTROL (*(reg32_t *)(USBHC_BASE_ADDR + 0x04))
1125 #define HC_CMD_STAT (*(reg32_t *)(USBHC_BASE_ADDR + 0x08))
1126 #define HC_INT_STAT (*(reg32_t *)(USBHC_BASE_ADDR + 0x0C))
1127 #define HC_INT_EN (*(reg32_t *)(USBHC_BASE_ADDR + 0x10))
1128 #define HC_INT_DIS (*(reg32_t *)(USBHC_BASE_ADDR + 0x14))
1129 #define HC_HCCA (*(reg32_t *)(USBHC_BASE_ADDR + 0x18))
1130 #define HC_PERIOD_CUR_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x1C))
1131 #define HC_CTRL_HEAD_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x20))
1132 #define HC_CTRL_CUR_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x24))
1133 #define HC_BULK_HEAD_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x28))
1134 #define HC_BULK_CUR_ED (*(reg32_t *)(USBHC_BASE_ADDR + 0x2C))
1135 #define HC_DONE_HEAD (*(reg32_t *)(USBHC_BASE_ADDR + 0x30))
1136 #define HC_FM_INTERVAL (*(reg32_t *)(USBHC_BASE_ADDR + 0x34))
1137 #define HC_FM_REMAINING (*(reg32_t *)(USBHC_BASE_ADDR + 0x38))
1138 #define HC_FM_NUMBER (*(reg32_t *)(USBHC_BASE_ADDR + 0x3C))
1139 #define HC_PERIOD_START (*(reg32_t *)(USBHC_BASE_ADDR + 0x40))
1140 #define HC_LS_THRHLD (*(reg32_t *)(USBHC_BASE_ADDR + 0x44))
1141 #define HC_RH_DESCA (*(reg32_t *)(USBHC_BASE_ADDR + 0x48))
1142 #define HC_RH_DESCB (*(reg32_t *)(USBHC_BASE_ADDR + 0x4C))
1143 #define HC_RH_STAT (*(reg32_t *)(USBHC_BASE_ADDR + 0x50))
1144 #define HC_RH_PORT_STAT1 (*(reg32_t *)(USBHC_BASE_ADDR + 0x54))
1145 #define HC_RH_PORT_STAT2 (*(reg32_t *)(USBHC_BASE_ADDR + 0x58))
1147 /* USB OTG Controller */
1148 #define USBOTG_BASE_ADDR 0xFFE0C100
1149 #define OTG_INT_STAT (*(reg32_t *)(USBOTG_BASE_ADDR + 0x00))
1150 #define OTG_INT_EN (*(reg32_t *)(USBOTG_BASE_ADDR + 0x04))
1151 #define OTG_INT_SET (*(reg32_t *)(USBOTG_BASE_ADDR + 0x08))
1152 #define OTG_INT_CLR (*(reg32_t *)(USBOTG_BASE_ADDR + 0x0C))
1153 /* On LPC23xx, the name is USBPortSel, on LPC24xx, the name is OTG_STAT_CTRL */
1154 #define OTG_STAT_CTRL (*(reg32_t *)(USBOTG_BASE_ADDR + 0x10))
1155 #define OTG_TIMER (*(reg32_t *)(USBOTG_BASE_ADDR + 0x14))
1157 #define USBOTG_I2C_BASE_ADDR 0xFFE0C300
1158 #define OTG_I2C_RX (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x00))
1159 #define OTG_I2C_TX (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x00))
1160 #define OTG_I2C_STS (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x04))
1161 #define OTG_I2C_CTL (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x08))
1162 #define OTG_I2C_CLKHI (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x0C))
1163 #define OTG_I2C_CLKLO (*(reg32_t *)(USBOTG_I2C_BASE_ADDR + 0x10))
1165 /* On LPC23xx, the names are USBClkCtrl and USBClkSt; on LPC24xx, the names are
1166 OTG_CLK_CTRL and OTG_CLK_STAT respectively. */
1167 #define USBOTG_CLK_BASE_ADDR 0xFFE0CFF0
1168 #define OTG_CLK_CTRL (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x04))
1169 #define OTG_CLK_STAT (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x08))
1171 /* Note: below three register name convention is for LPC23xx USB device only, match
1172 with the spec. update in USB Device Section. */
1173 #define USBPortSel (*(reg32_t *)(USBOTG_BASE_ADDR + 0x10))
1174 #define USBClkCtrl (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x04))
1175 #define USBClkSt (*(reg32_t *)(USBOTG_CLK_BASE_ADDR + 0x08))
1177 /* Ethernet MAC (32 bit data bus) -- all registers are RW unless indicated in parentheses */
1178 #define MAC_BASE_ADDR 0xFFE00000 /* AHB Peripheral # 0 */
1179 #define MAC_MAC1 (*(reg32_t *)(MAC_BASE_ADDR + 0x000)) /* MAC config reg 1 */
1180 #define MAC_MAC2 (*(reg32_t *)(MAC_BASE_ADDR + 0x004)) /* MAC config reg 2 */
1181 #define MAC_IPGT (*(reg32_t *)(MAC_BASE_ADDR + 0x008)) /* b2b InterPacketGap reg */
1182 #define MAC_IPGR (*(reg32_t *)(MAC_BASE_ADDR + 0x00C)) /* non b2b InterPacketGap reg */
1183 #define MAC_CLRT (*(reg32_t *)(MAC_BASE_ADDR + 0x010)) /* CoLlision window/ReTry reg */
1184 #define MAC_MAXF (*(reg32_t *)(MAC_BASE_ADDR + 0x014)) /* MAXimum Frame reg */
1185 #define MAC_SUPP (*(reg32_t *)(MAC_BASE_ADDR + 0x018)) /* PHY SUPPort reg */
1186 #define MAC_TEST (*(reg32_t *)(MAC_BASE_ADDR + 0x01C)) /* TEST reg */
1187 #define MAC_MCFG (*(reg32_t *)(MAC_BASE_ADDR + 0x020)) /* MII Mgmt ConFiG reg */
1188 #define MAC_MCMD (*(reg32_t *)(MAC_BASE_ADDR + 0x024)) /* MII Mgmt CoMmanD reg */
1189 #define MAC_MADR (*(reg32_t *)(MAC_BASE_ADDR + 0x028)) /* MII Mgmt ADdRess reg */
1190 #define MAC_MWTD (*(reg32_t *)(MAC_BASE_ADDR + 0x02C)) /* MII Mgmt WriTe Data reg (WO) */
1191 #define MAC_MRDD (*(reg32_t *)(MAC_BASE_ADDR + 0x030)) /* MII Mgmt ReaD Data reg (RO) */
1192 #define MAC_MIND (*(reg32_t *)(MAC_BASE_ADDR + 0x034)) /* MII Mgmt INDicators reg (RO) */
1194 #define MAC_SA0 (*(reg32_t *)(MAC_BASE_ADDR + 0x040)) /* Station Address 0 reg */
1195 #define MAC_SA1 (*(reg32_t *)(MAC_BASE_ADDR + 0x044)) /* Station Address 1 reg */
1196 #define MAC_SA2 (*(reg32_t *)(MAC_BASE_ADDR + 0x048)) /* Station Address 2 reg */
1198 #define MAC_COMMAND (*(reg32_t *)(MAC_BASE_ADDR + 0x100)) /* Command reg */
1199 #define MAC_STATUS (*(reg32_t *)(MAC_BASE_ADDR + 0x104)) /* Status reg (RO) */
1200 #define MAC_RXDESCRIPTOR (*(reg32_t *)(MAC_BASE_ADDR + 0x108)) /* Rx descriptor base address reg */
1201 #define MAC_RXSTATUS (*(reg32_t *)(MAC_BASE_ADDR + 0x10C)) /* Rx status base address reg */
1202 #define MAC_RXDESCRIPTORNUM (*(reg32_t *)(MAC_BASE_ADDR + 0x110)) /* Rx number of descriptors reg */
1203 #define MAC_RXPRODUCEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x114)) /* Rx produce index reg (RO) */
1204 #define MAC_RXCONSUMEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x118)) /* Rx consume index reg */
1205 #define MAC_TXDESCRIPTOR (*(reg32_t *)(MAC_BASE_ADDR + 0x11C)) /* Tx descriptor base address reg */
1206 #define MAC_TXSTATUS (*(reg32_t *)(MAC_BASE_ADDR + 0x120)) /* Tx status base address reg */
1207 #define MAC_TXDESCRIPTORNUM (*(reg32_t *)(MAC_BASE_ADDR + 0x124)) /* Tx number of descriptors reg */
1208 #define MAC_TXPRODUCEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x128)) /* Tx produce index reg */
1209 #define MAC_TXCONSUMEINDEX (*(reg32_t *)(MAC_BASE_ADDR + 0x12C)) /* Tx consume index reg (RO) */
1211 #define MAC_TSV0 (*(reg32_t *)(MAC_BASE_ADDR + 0x158)) /* Tx status vector 0 reg (RO) */
1212 #define MAC_TSV1 (*(reg32_t *)(MAC_BASE_ADDR + 0x15C)) /* Tx status vector 1 reg (RO) */
1213 #define MAC_RSV (*(reg32_t *)(MAC_BASE_ADDR + 0x160)) /* Rx status vector reg (RO) */
1215 #define MAC_FLOWCONTROLCNT (*(reg32_t *)(MAC_BASE_ADDR + 0x170)) /* Flow control counter reg */
1216 #define MAC_FLOWCONTROLSTS (*(reg32_t *)(MAC_BASE_ADDR + 0x174)) /* Flow control status reg */
1218 #define MAC_RXFILTERCTRL (*(reg32_t *)(MAC_BASE_ADDR + 0x200)) /* Rx filter ctrl reg */
1219 #define MAC_RXFILTERWOLSTS (*(reg32_t *)(MAC_BASE_ADDR + 0x204)) /* Rx filter WoL status reg (RO) */
1220 #define MAC_RXFILTERWOLCLR (*(reg32_t *)(MAC_BASE_ADDR + 0x208)) /* Rx filter WoL clear reg (WO) */
1222 #define MAC_HASHFILTERL (*(reg32_t *)(MAC_BASE_ADDR + 0x210)) /* Hash filter LSBs reg */
1223 #define MAC_HASHFILTERH (*(reg32_t *)(MAC_BASE_ADDR + 0x214)) /* Hash filter MSBs reg */
1225 #define MAC_INTSTATUS (*(reg32_t *)(MAC_BASE_ADDR + 0xFE0)) /* Interrupt status reg (RO) */
1226 #define MAC_INTENABLE (*(reg32_t *)(MAC_BASE_ADDR + 0xFE4)) /* Interrupt enable reg */
1227 #define MAC_INTCLEAR (*(reg32_t *)(MAC_BASE_ADDR + 0xFE8)) /* Interrupt clear reg (WO) */
1228 #define MAC_INTSET (*(reg32_t *)(MAC_BASE_ADDR + 0xFEC)) /* Interrupt set reg (WO) */
1230 #define MAC_POWERDOWN (*(reg32_t *)(MAC_BASE_ADDR + 0xFF4)) /* Power-down reg */
1231 #define MAC_MODULEID (*(reg32_t *)(MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
1240 #define INT_UART2 28
1241 #define INT_UART3 29
1243 #endif /* LPC23XX_H */