4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2004, 2005, 2006, 2007 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2004 Giovanni Bajo
34 * \brief CPU-specific attributes.
36 * \author Giovanni Bajo <rasky@develer.com>
37 * \author Bernie Innocenti <bernie@codewiz.org>
38 * \author Stefano Fedrigo <aleph@develer.com>
39 * \author Francesco Sacchi <batt@develer.com>
46 #include "cfg/cfg_attr.h" /* CONFIG_FAST_MEM */
47 #include "cfg/cfg_arch.h" /* ARCH_EMUL */
48 #include <cfg/compiler.h> /* for uintXX_t */
52 * \name Macros for determining CPU endianness.
55 #define CPU_BIG_ENDIAN 0x1234
56 #define CPU_LITTLE_ENDIAN 0x3412 /* Look twice, pal. This is not a bug. */
59 /** Macro to include cpu-specific versions of the headers. */
60 #define CPU_HEADER(module) PP_STRINGIZE(drv/PP_CAT3(module, _, CPU_ID).h)
62 /** Macro to include cpu-specific versions of implementation files. */
63 #define CPU_CSOURCE(module) PP_STRINGIZE(drv/PP_CAT3(module, _, CPU_ID).c)
68 #define NOP nop_instruction()
70 #define CPU_REG_BITS 16
71 #define CPU_REGS_CNT 16
72 #define CPU_STACK_GROWS_UPWARD 0
73 #define CPU_SP_ON_EMPTY_SLOT 0
74 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
77 /// Valid pointers should be >= than this value (used for debug)
78 #define CPU_RAM_START 0x100
82 #define NOP asm volatile ("nop")
84 #define CPU_REGS_CNT 7
85 #define CPU_SAVED_REGS_CNT 7
86 #define CPU_STACK_GROWS_UPWARD 0
87 #define CPU_SP_ON_EMPTY_SLOT 0
88 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
92 #define CPU_REG_BITS 64
95 /* WIN64 is an IL32-P64 weirdo. */
99 #define CPU_REG_BITS 32
102 /// Valid pointers should be >= than this value (used for debug)
103 #define CPU_RAM_START 0x1000
107 /* Register counts include SREG too */
108 #define CPU_REG_BITS 32
109 #define CPU_REGS_CNT 16
110 #define CPU_SAVED_REGS_CNT 9
111 #define CPU_STACK_GROWS_UPWARD 0
112 #define CPU_SP_ON_EMPTY_SLOT 0
113 #define CPU_HARVARD 0
115 /// Valid pointers should be >= than this value (used for debug)
116 #define CPU_RAM_START 0x200
118 #ifdef __IAR_SYSTEMS_ICC__
119 #warning Check CPU_BYTE_ORDER
120 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
122 #define NOP __no_operation()
124 #else /* GCC and compatibles */
126 #if defined(__ARMEB__)
127 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
128 #elif defined(__ARMEL__)
129 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
131 #error Unable to detect ARM endianness!
134 #define NOP asm volatile ("mov r0,r0" ::)
137 * Initialization value for registers in stack frame.
138 * The register index is not directly corrispondent to CPU
139 * register numbers, but is related to how are pushed to
140 * stack (\see asm_switch_context).
141 * Index (CPU_SAVED_REGS_CNT - 1) is the CPSR register,
142 * the initial value is set to:
143 * - All flags (N, Z, C, V) set to 0.
144 * - IRQ and FIQ enabled.
146 * - CPU in Supervisor Mode (SVC).
148 #define CPU_REG_INIT_VALUE(reg) (reg == (CPU_SAVED_REGS_CNT - 1) ? 0x13 : 0)
152 * Function attribute for use with performance critical code.
154 * On the AT91 family, code residing in flash has wait states.
155 * Moving functions to the data section is a quick & dirty way
156 * to get them transparently copied to SRAM for zero-wait-state
159 #define FAST_FUNC __attribute__((section(".data")))
162 * Data attribute to move constant data to fast memory storage.
166 #define FAST_RODATA __attribute__((section(".data")))
168 #else // !CONFIG_FAST_MEM
169 #define FAST_RODATA /**/
170 #define FAST_FUNC /**/
174 * Function attribute to declare an interrupt service routine.
176 #define ISR_FUNC __attribute__((interrupt))
178 #endif /* !__IAR_SYSTEMS_ICC_ */
181 #define NOP asm volatile ("nop" ::)
183 /* Register counts include SREG too */
184 #define CPU_REG_BITS (CPU_PPC32 ? 32 : 64)
185 #define CPU_REGS_CNT FIXME
186 #define CPU_SAVED_REGS_CNT 1 // FIXME
187 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
188 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
189 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
190 #define CPU_HARVARD 0
192 /// Valid pointers should be >= than this value (used for debug)
193 #define CPU_RAM_START 0x1000
199 #define CPU_REG_BITS 16
200 #define CPU_REGS_CNT FIXME
201 #define CPU_SAVED_REGS_CNT 8
202 #define CPU_STACK_GROWS_UPWARD 1
203 #define CPU_SP_ON_EMPTY_SLOT 0
204 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
205 #define CPU_HARVARD 1
207 /* Memory is word-addessed in the DSP56K */
208 #define CPU_BITS_PER_CHAR 16
209 #define SIZEOF_SHORT 1
211 #define SIZEOF_LONG 2
214 /// Valid pointers should be >= than this value (used for debug)
215 #define CPU_RAM_START 0x200
219 #define NOP asm volatile ("nop" ::)
221 /* Register counts include SREG too */
222 #define CPU_REG_BITS 8
223 #define CPU_REGS_CNT 33
224 #define CPU_SAVED_REGS_CNT 19
225 #define CPU_STACK_GROWS_UPWARD 0
226 #define CPU_SP_ON_EMPTY_SLOT 1
227 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
228 #define CPU_HARVARD 1
231 * Initialization value for registers in stack frame.
232 * The register index is not directly corrispondent to CPU
233 * register numbers. Index 0 is the SREG register: the initial
234 * value is all 0 but the interrupt bit (bit 7).
236 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
238 /// Valid pointers should be >= than this value (used for debug)
239 #define CPU_RAM_START 0x100
242 #error No CPU_... defined.
245 /// Default for macro not defined in the right arch section
246 #ifndef CPU_REG_INIT_VALUE
247 #define CPU_REG_INIT_VALUE(reg) 0
250 #ifndef CPU_STACK_GROWS_UPWARD
251 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
254 #ifndef CPU_SP_ON_EMPTY_SLOT
255 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
260 * Function attribute for use with performance critical code.
262 #define FAST_FUNC /* */
267 * Data attribute to move constant data to fast memory storage.
269 #define FAST_RODATA /* */
273 * Support stack handling peculiarities of a few CPUs.
275 * Most processors let their stack grow downward and
276 * keep SP pointing at the last pushed value.
278 #if !CPU_STACK_GROWS_UPWARD
279 #if !CPU_SP_ON_EMPTY_SLOT
280 /* Most microprocessors (x86, m68k...) */
281 #define CPU_PUSH_WORD(sp, data) \
282 do { *--(sp) = (data); } while (0)
283 #define CPU_POP_WORD(sp) \
287 #define CPU_PUSH_WORD(sp, data) \
288 do { *(sp)-- = (data); } while (0)
289 #define CPU_POP_WORD(sp) \
293 #else /* CPU_STACK_GROWS_UPWARD */
295 #if !CPU_SP_ON_EMPTY_SLOT
296 /* DSP56K and other weirdos */
297 #define CPU_PUSH_WORD(sp, data) \
298 do { *++(sp) = (cpustack_t)(data); } while (0)
299 #define CPU_POP_WORD(sp) \
302 #error I bet you cannot find a CPU like this
309 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
310 * RTS discards SR while returning (it does not restore it). So we push
311 * 0 to fake the same context.
313 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
315 CPU_PUSH_WORD((sp), (func)); \
316 CPU_PUSH_WORD((sp), 0x100); \
321 * On AVR, addresses are pushed into the stack as little-endian, while
322 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
323 * no natural endianess).
325 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
327 uint16_t funcaddr = (uint16_t)(func); \
328 CPU_PUSH_WORD((sp), funcaddr); \
329 CPU_PUSH_WORD((sp), funcaddr>>8); \
333 * If the kernel is in idle-spinning, the processor executes:
339 * IRQ_ENABLE is translated in asm as "sei" and IRQ_DISABLE as "cli".
340 * We could define CPU_IDLE to expand to none, so the resulting
346 * But Atmel datasheet states:
347 * "When using the SEI instruction to enable interrupts,
348 * the instruction following SEI will be executed *before*
349 * any pending interrupts", so "cli" is executed before any
350 * pending interrupt with the result that IRQs will *NOT*
352 * To ensure that IRQ will run a NOP is required.
357 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
358 CPU_PUSH_WORD((sp), (cpustack_t)(func))
364 * \brief Invoked by the scheduler to stop the CPU when idle.
366 * This hook can be redefined to put the CPU in low-power mode, or to
367 * profile system load with an external strobe, or to save CPU cycles
368 * in hosted environments such as emulators.
371 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
372 /* This emulator hook should yield the CPU to the host. */
374 void emul_idle(void);
376 #define CPU_IDLE emul_idle()
377 #else /* !ARCH_EMUL */
378 #define CPU_IDLE do { /* nothing */ } while (0)
379 #endif /* !ARCH_EMUL */
380 #endif /* !CPU_IDLE */
382 #endif /* CPU_ATTR_H */