4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2004, 2005, 2006, 2007 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2004 Giovanni Bajo
34 * \brief CPU-specific attributes.
36 * \author Giovanni Bajo <rasky@develer.com>
37 * \author Bernardo Innocenti <bernie@develer.com>
38 * \author Stefano Fedrigo <aleph@develer.com>
39 * \author Francesco Sacchi <batt@develer.com>
45 #include <cfg/compiler.h> /* for uintXX_t */
46 #include <cfg/arch_config.h> /* ARCH_EMUL */
48 #include "appconfig.h" // CONFIG_FAST_MEM
51 * \name Macros for determining CPU endianness.
54 #define CPU_BIG_ENDIAN 0x1234
55 #define CPU_LITTLE_ENDIAN 0x3412 /* Look twice, pal. This is not a bug. */
58 /** Macro to include cpu-specific versions of the headers. */
59 #define CPU_HEADER(module) PP_STRINGIZE(drv/PP_CAT3(module, _, CPU_ID).h)
61 /** Macro to include cpu-specific versions of implementation files. */
62 #define CPU_CSOURCE(module) PP_STRINGIZE(drv/PP_CAT3(module, _, CPU_ID).c)
67 #define NOP nop_instruction()
69 #define CPU_REG_BITS 16
70 #define CPU_REGS_CNT 16
71 #define CPU_STACK_GROWS_UPWARD 0
72 #define CPU_SP_ON_EMPTY_SLOT 0
73 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
78 #define NOP asm volatile ("nop")
80 #define CPU_REGS_CNT 7
81 #define CPU_SAVED_REGS_CNT 7
82 #define CPU_STACK_GROWS_UPWARD 0
83 #define CPU_SP_ON_EMPTY_SLOT 0
84 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
88 #define CPU_REG_BITS 64
91 /* WIN64 is an IL32-P64 weirdo. */
95 #define CPU_REG_BITS 32
100 /* Register counts include SREG too */
101 #define CPU_REG_BITS 32
102 #define CPU_REGS_CNT 16
103 #define CPU_SAVED_REGS_CNT 9
104 #define CPU_STACK_GROWS_UPWARD 0
105 #define CPU_SP_ON_EMPTY_SLOT 0
106 #define CPU_HARVARD 0
108 #ifdef __IAR_SYSTEMS_ICC__
109 #warning Check CPU_BYTE_ORDER
110 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
112 #define NOP __no_operation()
114 #else /* GCC and compatibles */
116 #if defined(__ARMEB__)
117 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
118 #elif defined(__ARMEL__)
119 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
121 #error Unable to detect ARM endianness!
124 #define NOP asm volatile ("mov r0,r0" ::)
127 * Initialization value for registers in stack frame.
128 * The register index is not directly corrispondent to CPU
129 * register numbers, but is related to how are pushed to
130 * stack (\see asm_switch_context).
131 * Index (CPU_SAVED_REGS_CNT - 1) is the CPSR register,
132 * the initial value is set to:
133 * - All flags (N, Z, C, V) set to 0.
134 * - IRQ and FIQ enabled.
136 * - CPU in Supervisor Mode (SVC).
138 #define CPU_REG_INIT_VALUE(reg) (reg == (CPU_SAVED_REGS_CNT - 1) ? 0x13 : 0)
142 * Function attribute for use with performance critical code.
144 * On the AT91 family, code residing in flash has wait states.
145 * Moving functions to the data section is a quick & dirty way
146 * to get them transparently copied to SRAM for zero-wait-state
149 #define FAST_FUNC __attribute__((section(".data")))
152 * Data attribute to move constant data to fast memory storage.
156 #define FAST_RODATA __attribute__((section(".data")))
158 #else // !CONFIG_FAST_MEM
159 #define FAST_RODATA /**/
160 #define FAST_FUNC /**/
164 * Function attribute to declare an interrupt service routine.
166 #define ISR_FUNC __attribute__((interrupt))
168 #endif /* !__IAR_SYSTEMS_ICC_ */
171 #define NOP asm volatile ("nop" ::)
173 /* Register counts include SREG too */
174 #define CPU_REG_BITS (CPU_PPC32 ? 32 : 64)
175 #define CPU_REGS_CNT FIXME
176 #define CPU_SAVED_REGS_CNT FIXME
177 #define CPU_STACK_GROWS_UPWARD 0 //FIXME
178 #define CPU_SP_ON_EMPTY_SLOT 0 //FIXME
179 #define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
180 #define CPU_HARVARD 0
186 #define CPU_REG_BITS 16
187 #define CPU_REGS_CNT FIXME
188 #define CPU_SAVED_REGS_CNT 8
189 #define CPU_STACK_GROWS_UPWARD 1
190 #define CPU_SP_ON_EMPTY_SLOT 0
191 #define CPU_BYTE_ORDER CPU_BIG_ENDIAN
192 #define CPU_HARVARD 1
194 /* Memory is word-addessed in the DSP56K */
195 #define CPU_BITS_PER_CHAR 16
196 #define SIZEOF_SHORT 1
198 #define SIZEOF_LONG 2
203 #define NOP asm volatile ("nop" ::)
205 /* Register counts include SREG too */
206 #define CPU_REG_BITS 8
207 #define CPU_REGS_CNT 33
208 #define CPU_SAVED_REGS_CNT 19
209 #define CPU_STACK_GROWS_UPWARD 0
210 #define CPU_SP_ON_EMPTY_SLOT 1
211 #define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
212 #define CPU_HARVARD 1
215 * Initialization value for registers in stack frame.
216 * The register index is not directly corrispondent to CPU
217 * register numbers. Index 0 is the SREG register: the initial
218 * value is all 0 but the interrupt bit (bit 7).
220 #define CPU_REG_INIT_VALUE(reg) (reg == 0 ? 0x80 : 0)
223 #error No CPU_... defined.
226 /// Default for macro not defined in the right arch section
227 #ifndef CPU_REG_INIT_VALUE
228 #define CPU_REG_INIT_VALUE(reg) 0
232 #ifndef CPU_STACK_GROWS_UPWARD
233 #error CPU_STACK_GROWS_UPWARD should have been defined to either 0 or 1
236 #ifndef CPU_SP_ON_EMPTY_SLOT
237 #error CPU_SP_ON_EMPTY_SLOT should have been defined to either 0 or 1
241 * Support stack handling peculiarities of a few CPUs.
243 * Most processors let their stack grow downward and
244 * keep SP pointing at the last pushed value.
246 #if !CPU_STACK_GROWS_UPWARD
247 #if !CPU_SP_ON_EMPTY_SLOT
248 /* Most microprocessors (x86, m68k...) */
249 #define CPU_PUSH_WORD(sp, data) \
250 do { *--(sp) = (data); } while (0)
251 #define CPU_POP_WORD(sp) \
255 #define CPU_PUSH_WORD(sp, data) \
256 do { *(sp)-- = (data); } while (0)
257 #define CPU_POP_WORD(sp) \
261 #else /* CPU_STACK_GROWS_UPWARD */
263 #if !CPU_SP_ON_EMPTY_SLOT
264 /* DSP56K and other weirdos */
265 #define CPU_PUSH_WORD(sp, data) \
266 do { *++(sp) = (cpustack_t)(data); } while (0)
267 #define CPU_POP_WORD(sp) \
270 #error I bet you cannot find a CPU like this
277 * DSP56k pushes both PC and SR to the stack in the JSR instruction, but
278 * RTS discards SR while returning (it does not restore it). So we push
279 * 0 to fake the same context.
281 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
283 CPU_PUSH_WORD((sp), (func)); \
284 CPU_PUSH_WORD((sp), 0x100); \
289 * In AVR, the addresses are pushed into the stack as little-endian, while
290 * memory accesses are big-endian (actually, it's a 8-bit CPU, so there is
291 * no natural endianess).
293 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
295 uint16_t funcaddr = (uint16_t)(func); \
296 CPU_PUSH_WORD((sp), funcaddr); \
297 CPU_PUSH_WORD((sp), funcaddr>>8); \
301 * If the kernel is in idle-spinning, the processor executes:
307 * IRQ_ENABLE is translated in asm as "sei" and IRQ_DISABLE as "cli".
308 * We could define CPU_IDLE to expand to none, so the resulting
314 * But Atmel datasheet states:
315 * "When using the SEI instruction to enable interrupts,
316 * the instruction following SEI will be executed *before*
317 * any pending interrupts", so "cli" is executed before any
318 * pending interrupt with the result that IRQs will *NOT*
320 * To ensure that IRQ will run a NOP is required.
325 #define CPU_PUSH_CALL_CONTEXT(sp, func) \
326 CPU_PUSH_WORD((sp), (cpustack_t)(func))
332 * \brief Invoked by the scheduler to stop the CPU when idle.
334 * This hook can be redefined to put the CPU in low-power mode, or to
335 * profile system load with an external strobe, or to save CPU cycles
336 * in hosted environments such as emulators.
339 #if defined(ARCH_EMUL) && (ARCH & ARCH_EMUL)
340 /* This emulator hook should yield the CPU to the host. */
342 void emul_idle(void);
344 #define CPU_IDLE emul_idle()
345 #else /* !ARCH_EMUL */
346 #define CPU_IDLE do { /* nothing */ } while (0)
347 #endif /* !ARCH_EMUL */
348 #endif /* !CPU_IDLE */
350 #endif /* CPU_ATTR_H */