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29 * Copyright 2003, 2004, 2005 Develer S.r.l. (http://www.develer.com/)
33 * \brief Driver for the AVR ATMega TWI (implementation)
35 * \author Stefano Fedrigo <aleph@develer.com>
36 * \author Bernie Innocenti <bernie@codewiz.org>
37 * \author Daniele Basile <asterix@develer.com>
41 #include "cfg/cfg_i2c.h"
43 #include <hw/hw_cpufreq.h> /* CPU_FREQ */
45 #define LOG_LEVEL I2C_LOG_LEVEL
46 #define LOG_FORMAT I2C_LOG_FORMAT
50 #include <cfg/debug.h>
51 #include <cfg/macros.h> // BV()
52 #include <cfg/module.h>
54 #include <cpu/detect.h>
56 #include <drv/timer.h>
59 #include <cpu/power.h>
61 #include <compat/twi.h>
63 #if !CONFIG_I2C_DISABLE_OLD_API
65 /* Wait for TWINT flag set: bus is ready */
66 #define WAIT_TWI_READY do {} while (!(TWCR & BV(TWINT)))
69 * Send START condition on the bus.
71 * \return true on success, false otherwise.
73 static bool i2c_builtin_start(void)
75 TWCR = BV(TWINT) | BV(TWSTA) | BV(TWEN);
78 if (TW_STATUS == TW_START || TW_STATUS == TW_REP_START)
81 LOG_ERR("!TW_(REP)START: %x\n", TWSR);
87 * Send START condition and select slave for write.
88 * \c id is the device id comprehensive of address left shifted by 1.
89 * The LSB of \c id is ignored and reset to 0 for write operation.
91 * \return true on success, false otherwise.
93 bool i2c_builtin_start_w(uint8_t id)
96 * Loop on the select write sequence: when the eeprom is busy
97 * writing previously sent data it will reply to the SLA_W
98 * control byte with a NACK. In this case, we must
99 * keep trying until the eeprom responds with an ACK.
101 ticks_t start = timer_clock();
102 while (i2c_builtin_start())
104 TWDR = id & ~I2C_READBIT;
105 TWCR = BV(TWINT) | BV(TWEN);
108 if (TW_STATUS == TW_MT_SLA_ACK)
110 else if (TW_STATUS != TW_MT_SLA_NACK)
112 LOG_ERR("!TW_MT_SLA_(N)ACK: %x\n", TWSR);
115 else if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
117 LOG_ERR("Timeout on TWI_MT_START\n");
127 * Send START condition and select slave for read.
128 * \c id is the device id comprehensive of address left shifted by 1.
129 * The LSB of \c id is ignored and set to 1 for read operation.
131 * \return true on success, false otherwise.
133 bool i2c_builtin_start_r(uint8_t id)
135 if (i2c_builtin_start())
137 TWDR = id | I2C_READBIT;
138 TWCR = BV(TWINT) | BV(TWEN);
141 if (TW_STATUS == TW_MR_SLA_ACK)
144 LOG_ERR("!TW_MR_SLA_ACK: %x\n", TWSR);
152 * Send STOP condition.
154 void i2c_builtin_stop(void)
156 TWCR = BV(TWINT) | BV(TWEN) | BV(TWSTO);
161 * Put a single byte in master transmitter mode
162 * to the selected slave device through the TWI bus.
164 * \return true on success, false on error.
166 bool i2c_builtin_put(const uint8_t data)
169 TWCR = BV(TWINT) | BV(TWEN);
171 if (TW_STATUS != TW_MT_DATA_ACK)
173 LOG_ERR("!TW_MT_DATA_ACK: %x\n", TWSR);
180 * Get 1 byte from slave in master transmitter mode
181 * to the selected slave device through the TWI bus.
182 * If \a ack is true issue a ACK after getting the byte,
183 * otherwise a NACK is issued.
185 * \return the byte read if ok, EOF on errors.
187 int i2c_builtin_get(bool ack)
189 TWCR = BV(TWINT) | BV(TWEN) | (ack ? BV(TWEA) : 0);
194 if (TW_STATUS != TW_MR_DATA_ACK)
196 LOG_ERR("!TW_MR_DATA_ACK: %x\n", TWSR);
202 if (TW_STATUS != TW_MR_DATA_NACK)
204 LOG_ERR("!TW_MR_DATA_NACK: %x\n", TWSR);
209 /* avoid sign extension */
210 return (int)(uint8_t)TWDR;
217 * Initialize TWI module.
219 void i2c_builtin_init(void)
223 * This is pretty useless according to AVR's datasheet,
224 * but it helps us driving the TWI data lines on boards
225 * where the bus pull-up resistors are missing. This is
226 * probably due to some unwanted interaction between the
227 * port pin and the TWI lines.
229 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
230 PORTD |= BV(PD0) | BV(PD1);
231 DDRD |= BV(PD0) | BV(PD1);
232 #elif CPU_AVR_ATMEGA8
233 PORTC |= BV(PC4) | BV(PC5);
234 DDRC |= BV(PC4) | BV(PC5);
235 #elif CPU_AVR_ATMEGA32
236 PORTC |= BV(PC1) | BV(PC0);
237 DDRC |= BV(PC1) | BV(PC0);
239 #error Unsupported architecture
244 * F = CPU_FREQ / (16 + 2*TWBR * 4^TWPS)
246 #ifndef CONFIG_I2C_FREQ
247 #warning Using default value of 300000L for CONFIG_I2C_FREQ
248 #define CONFIG_I2C_FREQ 300000L /* ~300 kHz */
250 #define TWI_PRESC 1 /* 4 ^ TWPS */
252 TWBR = (CPU_FREQ / (2 * CONFIG_I2C_FREQ * TWI_PRESC)) - (8 / TWI_PRESC);
259 #endif /* !CONFIG_I2C_DISABLE_OLD_API */
269 /* Wait for TWINT flag set: bus is ready */
270 #define WAIT_READY() \
272 while (!(TWCR & BV(TWINT))) \
277 * Send START condition on the bus.
279 INLINE bool i2c_hw_start(void)
281 TWCR = BV(TWINT) | BV(TWSTA) | BV(TWEN);
284 if (TW_STATUS == TW_START || TW_STATUS == TW_REP_START)
291 * Send STOP condition.
293 INLINE void i2c_hw_stop(void)
295 TWCR = BV(TWINT) | BV(TWEN) | BV(TWSTO);
298 static void i2c_avr_start(I2c *i2c, uint16_t slave_addr)
301 * Loop on the select write sequence: when the eeprom is busy
302 * writing previously sent data it will reply to the SLA_W
303 * control byte with a NACK. In this case, we must
304 * keep trying until the slave responds with an ACK.
306 ticks_t start = timer_clock();
307 while (i2c_hw_start())
310 uint8_t sla_nack = 0;
311 if (I2C_TEST_START(i2c->flags) == I2C_START_W)
313 TWDR = slave_addr & ~I2C_READBIT;
314 sla_ack = TW_MT_SLA_ACK;
315 sla_nack = TW_MT_SLA_NACK;
319 TWDR = slave_addr | I2C_READBIT;
320 sla_ack = TW_MR_SLA_ACK;
321 sla_nack = TW_MR_SLA_NACK;
324 TWCR = BV(TWINT) | BV(TWEN);
327 if (TW_STATUS == sla_ack)
329 else if (TW_STATUS != sla_nack)
331 LOG_ERR("Start addr NACK[%x]\n", TWSR);
332 i2c->errors |= I2C_NO_ACK;
336 else if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
338 LOG_ERR("Start timeout\n");
339 i2c->errors |= I2C_START_TIMEOUT;
345 LOG_ERR("I2c error\n");
346 i2c->errors |= I2C_ERR;
350 static void i2c_avr_putc(I2c *i2c, const uint8_t data)
354 TWCR = BV(TWINT) | BV(TWEN);
357 if (TW_STATUS != TW_MT_DATA_ACK)
359 LOG_ERR("Data nack[%x]\n", TWSR);
360 i2c->errors |= I2C_DATA_NACK;
364 if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
368 static uint8_t i2c_avr_getc(I2c *i2c)
370 uint8_t data_flag = 0;
371 if (i2c->xfer_size == 1)
373 TWCR = BV(TWINT) | BV(TWEN);
374 data_flag = TW_MR_DATA_NACK;
378 TWCR = BV(TWINT) | BV(TWEN) | BV(TWEA);
379 data_flag = TW_MR_DATA_ACK;
384 if (TW_STATUS != data_flag)
386 LOG_ERR("Data nack[%x]\n", TWSR);
387 i2c->errors |= I2C_DATA_NACK;
395 if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
402 static const I2cVT i2c_avr_vt =
404 .start = i2c_avr_start,
405 .getc = i2c_avr_getc,
406 .putc = i2c_avr_putc,
407 .write = i2c_genericWrite,
408 .read = i2c_genericRead,
411 struct I2cHardware i2c_avr_hw[] =
418 * Initialize I2C module.
420 void i2c_hw_init(I2c *i2c, int dev, uint32_t clock)
422 i2c->hw = &i2c_avr_hw[dev];
423 i2c->vt = &i2c_avr_vt;
427 * This is pretty useless according to AVR's datasheet,
428 * but it helps us driving the TWI data lines on boards
429 * where the bus pull-up resistors are missing. This is
430 * probably due to some unwanted interaction between the
431 * port pin and the TWI lines.
433 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
434 PORTD |= BV(PD0) | BV(PD1);
435 DDRD |= BV(PD0) | BV(PD1);
436 #elif CPU_AVR_ATMEGA8
437 PORTC |= BV(PC4) | BV(PC5);
438 DDRC |= BV(PC4) | BV(PC5);
439 #elif CPU_AVR_ATMEGA32
440 PORTC |= BV(PC1) | BV(PC0);
441 DDRC |= BV(PC1) | BV(PC0);
443 #error Unsupported architecture
448 * F = CPU_FREQ / (16 + 2*TWBR * 4^TWPS)
451 #define TWI_PRESC 1 /* 4 ^ TWPS */
453 TWBR = (CPU_FREQ / (2 * clock * TWI_PRESC)) - (8 / TWI_PRESC);