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29 * Copyright 2003, 2004, 2005 Develer S.r.l. (http://www.develer.com/)
33 * \brief Driver for the AVR ATMega TWI (implementation)
35 * \author Stefano Fedrigo <aleph@develer.com>
36 * \author Bernie Innocenti <bernie@codewiz.org>
39 #include <hw/hw_cpufreq.h> /* CPU_FREQ */
41 #include "cfg/cfg_i2c.h"
43 #define LOG_LEVEL I2C_LOG_LEVEL
44 #define LOG_FORMAT I2C_LOG_FORMAT
48 #include <cfg/debug.h>
49 #include <cfg/macros.h> // BV()
50 #include <cfg/module.h>
52 #include <cpu/detect.h>
54 #include <drv/timer.h>
57 #include <compat/twi.h>
65 /* Wait for TWINT flag set: bus is ready */
66 #define WAIT_TWI_READY do {} while (!(TWCR & BV(TWINT)))
69 * Send START condition on the bus.
71 * \return true on success, false otherwise.
73 static bool i2c_builtin_start(void)
75 TWCR = BV(TWINT) | BV(TWSTA) | BV(TWEN);
78 if (TW_STATUS == TW_START || TW_STATUS == TW_REP_START)
81 LOG_ERR("!TW_(REP)START: %x\n", TWSR);
87 * Send START condition and select slave for write.
88 * \c id is the device id comprehensive of address left shifted by 1.
89 * The LSB of \c id is ignored and reset to 0 for write operation.
91 * \return true on success, false otherwise.
93 bool i2c_builtin_start_w(uint8_t id)
96 * Loop on the select write sequence: when the eeprom is busy
97 * writing previously sent data it will reply to the SLA_W
98 * control byte with a NACK. In this case, we must
99 * keep trying until the eeprom responds with an ACK.
101 ticks_t start = timer_clock();
102 while (i2c_builtin_start())
104 TWDR = id & ~I2C_READBIT;
105 TWCR = BV(TWINT) | BV(TWEN);
108 if (TW_STATUS == TW_MT_SLA_ACK)
110 else if (TW_STATUS != TW_MT_SLA_NACK)
112 LOG_ERR("!TW_MT_SLA_(N)ACK: %x\n", TWSR);
115 else if (timer_clock() - start > ms_to_ticks(CONFIG_I2C_START_TIMEOUT))
117 LOG_ERR("Timeout on TWI_MT_START\n");
127 * Send START condition and select slave for read.
128 * \c id is the device id comprehensive of address left shifted by 1.
129 * The LSB of \c id is ignored and set to 1 for read operation.
131 * \return true on success, false otherwise.
133 bool i2c_builtin_start_r(uint8_t id)
135 if (i2c_builtin_start())
137 TWDR = id | I2C_READBIT;
138 TWCR = BV(TWINT) | BV(TWEN);
141 if (TW_STATUS == TW_MR_SLA_ACK)
144 LOG_ERR("!TW_MR_SLA_ACK: %x\n", TWSR);
152 * Send STOP condition.
154 void i2c_builtin_stop(void)
156 TWCR = BV(TWINT) | BV(TWEN) | BV(TWSTO);
161 * Put a single byte in master transmitter mode
162 * to the selected slave device through the TWI bus.
164 * \return true on success, false on error.
166 bool i2c_builtin_put(const uint8_t data)
169 TWCR = BV(TWINT) | BV(TWEN);
171 if (TW_STATUS != TW_MT_DATA_ACK)
173 LOG_ERR("!TW_MT_DATA_ACK: %x\n", TWSR);
180 * Get 1 byte from slave in master transmitter mode
181 * to the selected slave device through the TWI bus.
182 * If \a ack is true issue a ACK after getting the byte,
183 * otherwise a NACK is issued.
185 * \return the byte read if ok, EOF on errors.
187 int i2c_builtin_get(bool ack)
189 TWCR = BV(TWINT) | BV(TWEN) | (ack ? BV(TWEA) : 0);
194 if (TW_STATUS != TW_MR_DATA_ACK)
196 LOG_ERR("!TW_MR_DATA_ACK: %x\n", TWSR);
202 if (TW_STATUS != TW_MR_DATA_NACK)
204 LOG_ERR("!TW_MR_DATA_NACK: %x\n", TWSR);
209 /* avoid sign extension */
210 return (int)(uint8_t)TWDR;
215 static void i2c_avr_start(struct I2c *i2c, uint16_t slave_addr)
217 if (I2C_TEST_START(i2c->flags) == I2C_START_W)
219 if (i2c_builtin_start_w(slave_addr))
221 LOG_ERR("Start timeout\n");
222 i2c->errors |= I2C_START_TIMEOUT;
225 else /* (I2C_TEST_START(i2c->flags) == I2C_START_R) */
227 if (i2c_builtin_start_r(slave_addr))
229 LOG_ERR("Start r no ACK\n");
230 i2c->errors |= I2C_NO_ACK;
235 static void i2c_avr_put(I2c *i2c, const uint8_t data)
237 if (i2c_builtin_put(data))
239 LOG_ERR("Start r no ACK\n");
240 i2c->errors |= I2C_DATA_NACK;
243 if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
247 static uint8_t i2c_avr_get(I2c *i2c)
250 if (i2c->xfer_size == 1)
253 uint8_t data = i2c_builtin_get(ack);
255 if ((i2c->xfer_size == 1) && (I2C_TEST_STOP(i2c->flags) == I2C_STOP))
265 * Initialize TWI module.
267 INLINE void i2c_avr_init(uint32_t clock)
271 * This is pretty useless according to AVR's datasheet,
272 * but it helps us driving the TWI data lines on boards
273 * where the bus pull-up resistors are missing. This is
274 * probably due to some unwanted interaction between the
275 * port pin and the TWI lines.
277 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
278 PORTD |= BV(PD0) | BV(PD1);
279 DDRD |= BV(PD0) | BV(PD1);
280 #elif CPU_AVR_ATMEGA8
281 PORTC |= BV(PC4) | BV(PC5);
282 DDRC |= BV(PC4) | BV(PC5);
283 #elif CPU_AVR_ATMEGA32
284 PORTC |= BV(PC1) | BV(PC0);
285 DDRC |= BV(PC1) | BV(PC0);
287 #error Unsupported architecture
292 * F = CPU_FREQ / (16 + 2*TWBR * 4^TWPS)
295 #define TWI_PRESC 1 /* 4 ^ TWPS */
297 TWBR = (CPU_FREQ / (2 * clock * TWI_PRESC)) - (8 / TWI_PRESC);
305 static const I2cVT i2c_lm3s_vt =
307 .start = i2c_avr_start,
314 struct I2cHardware i2c_avr_hw[] =
321 * Initialize I2C module.
323 void i2c_hw_init(I2c *i2c, int dev, uint32_t clock)
325 i2c->hw = &i2c_avr_hw[dev];
326 i2c->vt = &i2c_avr_vt;
331 void i2c_bitbang_init(void)
333 i2c_avr_init(CONFIG_I2C_FREQ);