4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2003, 2004, 2010 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2000 Bernie Innocenti <bernie@codewiz.org>
34 * \brief AVR UART and SPI I/O driver (Implementation)
36 * \author Bernie Innocenti <bernie@codewiz.org>
37 * \author Stefano Fedrigo <aleph@develer.com>
38 * \author Luca Ottaviano <lottaviano@develer.com>
41 #include "hw/hw_ser.h" /* Required for bus macros overrides */
42 #include <hw/hw_cpufreq.h> /* CPU_FREQ */
44 #include "cfg/cfg_ser.h"
46 #include <cfg/macros.h> /* DIV_ROUND */
47 #include <cfg/debug.h>
48 #include <cfg/cfg_arch.h> // ARCH_NIGHTTEST
51 #include <drv/ser_p.h>
52 #include <drv/timer.h>
54 #include <struct/fifobuf.h>
58 #if defined(__AVR_LIBC_VERSION__) && (__AVR_LIBC_VERSION__ >= 10400UL)
59 #include <avr/interrupt.h>
61 #include <avr/signal.h>
65 #if !CONFIG_SER_HWHANDSHAKE
67 * \name Hardware handshake (RTS/CTS).
70 #define RTS_ON do {} while (0)
71 #define RTS_OFF do {} while (0)
72 #define IS_CTS_ON true
73 #define EIMSKF_CTS 0 /**< Dummy value, must be overridden */
77 #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280
78 #define BIT_RXCIE0 RXCIE0
79 #define BIT_RXEN0 RXEN0
80 #define BIT_TXEN0 TXEN0
81 #define BIT_UDRIE0 UDRIE0
83 #define BIT_RXCIE1 RXCIE1
84 #define BIT_RXEN1 RXEN1
85 #define BIT_TXEN1 TXEN1
86 #define BIT_UDRIE1 UDRIE1
87 #if CPU_AVR_ATMEGA1280
88 #define BIT_RXCIE2 RXCIE2
89 #define BIT_RXEN2 RXEN2
90 #define BIT_TXEN2 TXEN2
91 #define BIT_UDRIE2 UDRIE2
93 #define BIT_RXCIE3 RXCIE3
94 #define BIT_RXEN3 RXEN3
95 #define BIT_TXEN3 TXEN3
96 #define BIT_UDRIE3 UDRIE3
98 #elif CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
99 #define BIT_RXCIE0 RXCIE0
100 #define BIT_RXEN0 RXEN0
101 #define BIT_TXEN0 TXEN0
102 #define BIT_UDRIE0 UDRIE0
104 #define BIT_RXCIE1 RXCIE0
105 #define BIT_RXEN1 RXEN0
106 #define BIT_TXEN1 TXEN0
107 #define BIT_UDRIE1 UDRIE0
109 #define BIT_RXCIE0 RXCIE
110 #define BIT_RXEN0 RXEN
111 #define BIT_TXEN0 TXEN
112 #define BIT_UDRIE0 UDRIE
114 #define BIT_RXCIE1 RXCIE
115 #define BIT_RXEN1 RXEN
116 #define BIT_TXEN1 TXEN
117 #define BIT_UDRIE1 UDRIE
122 * \name Overridable serial bus hooks
124 * These can be redefined in hw.h to implement
125 * special bus policies such as half-duplex, 485, etc.
129 * TXBEGIN TXCHAR TXEND TXOFF
130 * | __________|__________ | |
133 * ______ __ __ __ __ __ __ ________________
134 * \/ \/ \/ \/ \/ \/ \/
135 * ______/\__/\__/\__/\__/\__/\__/
141 #ifndef SER_UART0_BUS_TXINIT
143 * Default TXINIT macro - invoked in uart0_init()
145 * - Enable both the receiver and the transmitter
146 * - Enable only the RX complete interrupt
148 #define SER_UART0_BUS_TXINIT do { \
149 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
153 #ifndef SER_UART0_BUS_TXBEGIN
155 * Invoked before starting a transmission
157 * - Enable both the receiver and the transmitter
158 * - Enable both the RX complete and UDR empty interrupts
160 #define SER_UART0_BUS_TXBEGIN do { \
161 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
165 #ifndef SER_UART0_BUS_TXCHAR
167 * Invoked to send one character.
169 #define SER_UART0_BUS_TXCHAR(c) do { \
174 #ifndef SER_UART0_BUS_TXEND
176 * Invoked as soon as the txfifo becomes empty
178 * - Keep both the receiver and the transmitter enabled
179 * - Keep the RX complete interrupt enabled
180 * - Disable the UDR empty interrupt
182 #define SER_UART0_BUS_TXEND do { \
183 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
187 #ifndef SER_UART0_BUS_TXOFF
189 * \def SER_UART0_BUS_TXOFF
191 * Invoked after the last character has been transmitted
193 * The default is no action.
196 #define SER_UART0_BUS_TXOFF
200 #ifndef SER_UART1_BUS_TXINIT
201 /** \sa SER_UART0_BUS_TXINIT */
202 #define SER_UART1_BUS_TXINIT do { \
203 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
206 #ifndef SER_UART1_BUS_TXBEGIN
207 /** \sa SER_UART0_BUS_TXBEGIN */
208 #define SER_UART1_BUS_TXBEGIN do { \
209 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
212 #ifndef SER_UART1_BUS_TXCHAR
213 /** \sa SER_UART0_BUS_TXCHAR */
214 #define SER_UART1_BUS_TXCHAR(c) do { \
218 #ifndef SER_UART1_BUS_TXEND
219 /** \sa SER_UART0_BUS_TXEND */
220 #define SER_UART1_BUS_TXEND do { \
221 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
224 #ifndef SER_UART1_BUS_TXOFF
226 * \def SER_UART1_BUS_TXOFF
228 * \see SER_UART0_BUS_TXOFF
231 #define SER_UART1_BUS_TXOFF
235 #ifndef SER_UART2_BUS_TXINIT
236 /** \sa SER_UART0_BUS_TXINIT */
237 #define SER_UART2_BUS_TXINIT do { \
238 UCSR2B = BV(BIT_RXCIE2) | BV(BIT_RXEN2) | BV(BIT_TXEN2); \
241 #ifndef SER_UART2_BUS_TXBEGIN
242 /** \sa SER_UART0_BUS_TXBEGIN */
243 #define SER_UART2_BUS_TXBEGIN do { \
244 UCSR2B = BV(BIT_RXCIE2) | BV(BIT_UDRIE2) | BV(BIT_RXEN2) | BV(BIT_TXEN2); \
247 #ifndef SER_UART2_BUS_TXCHAR
248 /** \sa SER_UART0_BUS_TXCHAR */
249 #define SER_UART2_BUS_TXCHAR(c) do { \
253 #ifndef SER_UART2_BUS_TXEND
254 /** \sa SER_UART0_BUS_TXEND */
255 #define SER_UART2_BUS_TXEND do { \
256 UCSR2B = BV(BIT_RXCIE2) | BV(BIT_RXEN2) | BV(BIT_TXEN2); \
259 #ifndef SER_UART2_BUS_TXOFF
261 * \def SER_UART2_BUS_TXOFF
263 * \see SER_UART0_BUS_TXOFF
266 #define SER_UART2_BUS_TXOFF
270 #ifndef SER_UART3_BUS_TXINIT
271 /** \sa SER_UART0_BUS_TXINIT */
272 #define SER_UART3_BUS_TXINIT do { \
273 UCSR3B = BV(BIT_RXCIE3) | BV(BIT_RXEN3) | BV(BIT_TXEN3); \
276 #ifndef SER_UART3_BUS_TXBEGIN
277 /** \sa SER_UART0_BUS_TXBEGIN */
278 #define SER_UART3_BUS_TXBEGIN do { \
279 UCSR3B = BV(BIT_RXCIE3) | BV(BIT_UDRIE3) | BV(BIT_RXEN3) | BV(BIT_TXEN3); \
282 #ifndef SER_UART3_BUS_TXCHAR
283 /** \sa SER_UART0_BUS_TXCHAR */
284 #define SER_UART3_BUS_TXCHAR(c) do { \
288 #ifndef SER_UART3_BUS_TXEND
289 /** \sa SER_UART0_BUS_TXEND */
290 #define SER_UART3_BUS_TXEND do { \
291 UCSR3B = BV(BIT_RXCIE3) | BV(BIT_RXEN3) | BV(BIT_TXEN3); \
294 #ifndef SER_UART3_BUS_TXOFF
296 * \def SER_UART3_BUS_TXOFF
298 * \see SER_UART0_BUS_TXOFF
301 #define SER_UART3_BUS_TXOFF
308 * \name Overridable SPI hooks
310 * These can be redefined in hw.h to implement
311 * special bus policies such as slave select pin handling, etc.
315 #ifndef SER_SPI_BUS_TXINIT
317 * Default TXINIT macro - invoked in spi_init()
318 * The default is no action.
320 #define SER_SPI_BUS_TXINIT
323 #ifndef SER_SPI_BUS_TXCLOSE
325 * Invoked after the last character has been transmitted.
326 * The default is no action.
328 #define SER_SPI_BUS_TXCLOSE
333 /* SPI port and pin configuration */
334 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 || CPU_AVR_ATMEGA1281 \
335 || CPU_AVR_ATMEGA1280
336 #define SPI_PORT PORTB
338 #define SPI_SS_BIT PB0
339 #define SPI_SCK_BIT PB1
340 #define SPI_MOSI_BIT PB2
341 #define SPI_MISO_BIT PB3
342 // TODO: these bits are the same as ATMEGA8 but the defines in avr-gcc are different.
343 // They should be the same!
344 #elif CPU_AVR_ATMEGA328P
345 #define SPI_PORT PORTB
347 #define SPI_SS_BIT PORTB2
348 #define SPI_SCK_BIT PORTB5
349 #define SPI_MOSI_BIT PORTB3
350 #define SPI_MISO_BIT PORTB4
351 #elif CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA168
352 #define SPI_PORT PORTB
354 #define SPI_SS_BIT PB2
355 #define SPI_SCK_BIT PB5
356 #define SPI_MOSI_BIT PB3
357 #define SPI_MISO_BIT PB4
358 #elif CPU_AVR_ATMEGA32
359 #define SPI_PORT PORTB
361 #define SPI_SS_BIT PB4
362 #define SPI_SCK_BIT PB7
363 #define SPI_MOSI_BIT PB5
364 #define SPI_MISO_BIT PB6
366 #error Unknown architecture
369 /* USART register definitions */
370 #if CPU_AVR_ATMEGA1280
371 #define AVR_HAS_UART1 1
372 #define AVR_HAS_UART2 1
373 #define AVR_HAS_UART3 1
374 #elif CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
375 #define AVR_HAS_UART1 1
376 #define AVR_HAS_UART2 0
377 #define AVR_HAS_UART3 0
378 #elif CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
379 #define AVR_HAS_UART1 0
380 #define AVR_HAS_UART2 0
381 #define AVR_HAS_UART3 0
382 #define USART0_UDRE_vect USART_UDRE_vect
383 #define USART0_RX_vect USART_RX_vect
384 #define USART0_TX_vect USART_TX_vect
385 #elif CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA32
386 #define AVR_HAS_UART1 0
387 #define AVR_HAS_UART2 0
388 #define AVR_HAS_UART3 0
397 #define USART0_UDRE_vect USART_UDRE_vect
398 #define USART0_RX_vect USART_RXC_vect
399 #define USART0_TX_vect USART_TXC_vect
400 #elif CPU_AVR_ATMEGA103
401 #define AVR_HAS_UART1 0
402 #define AVR_HAS_UART2 0
403 #define AVR_HAS_UART3 0
408 #define USART0_UDRE_vect USART_UDRE_vect
409 #define USART0_RX_vect USART_RX_vect
410 #define USART0_TX_vect USART_TX_vect
412 #error Unknown architecture
416 /* From the high-level serial driver */
417 extern struct Serial *ser_handles[SER_CNT];
419 /* TX and RX buffers */
420 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
421 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
423 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
424 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
427 static unsigned char uart2_txbuffer[CONFIG_UART2_TXBUFSIZE];
428 static unsigned char uart2_rxbuffer[CONFIG_UART2_RXBUFSIZE];
431 static unsigned char uart3_txbuffer[CONFIG_UART3_TXBUFSIZE];
432 static unsigned char uart3_rxbuffer[CONFIG_UART3_RXBUFSIZE];
434 static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
435 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
439 * Internal hardware state structure
441 * The \a sending variable is true while the transmission
442 * interrupt is retriggering itself.
444 * For the USARTs the \a sending flag is useful for taking specific
445 * actions before sending a burst of data, at the start of a trasmission
446 * but not before every char sent.
448 * For the SPI, this flag is necessary because the SPI sends and receives
449 * bytes at the same time and the SPI IRQ is unique for send/receive.
450 * The only way to start transmission is to write data in SPDR (this
451 * is done by spi_starttx()). We do this *only* if a transfer is
452 * not already started.
456 struct SerialHardware hw;
457 volatile bool sending;
465 static void uart0_init(
466 UNUSED_ARG(struct SerialHardware *, _hw),
467 UNUSED_ARG(struct Serial *, ser))
469 SER_UART0_BUS_TXINIT;
474 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
479 static void uart0_enabletxirq(struct SerialHardware *_hw)
481 struct AvrSerial *hw = (struct AvrSerial *)_hw;
484 * WARNING: racy code here! The tx interrupt sets hw->sending to false
485 * when it runs with an empty fifo. The order of statements in the
491 SER_UART0_BUS_TXBEGIN;
495 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
497 /* Compute baud-rate period */
498 uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1;
500 #if !CPU_AVR_ATMEGA103
501 UBRR0H = (period) >> 8;
505 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
508 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
510 #if !CPU_AVR_ATMEGA103
511 UCSR0C = (UCSR0C & ~(BV(UPM01) | BV(UPM00))) | ((parity) << UPM00);
517 static void uart1_init(
518 UNUSED_ARG(struct SerialHardware *, _hw),
519 UNUSED_ARG(struct Serial *, ser))
521 SER_UART1_BUS_TXINIT;
526 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
531 static void uart1_enabletxirq(struct SerialHardware *_hw)
533 struct AvrSerial *hw = (struct AvrSerial *)_hw;
536 * WARNING: racy code here! The tx interrupt
537 * sets hw->sending to false when it runs with
538 * an empty fifo. The order of the statements
539 * in the if-block matters.
544 SER_UART1_BUS_TXBEGIN;
548 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
550 /* Compute baud-rate period */
551 uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1;
553 UBRR1H = (period) >> 8;
556 //DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
559 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
561 UCSR1C = (UCSR1C & ~(BV(UPM11) | BV(UPM10))) | ((parity) << UPM10);
564 #endif // AVR_HAS_UART1
568 static void uart2_init(
569 UNUSED_ARG(struct SerialHardware *, _hw),
570 UNUSED_ARG(struct Serial *, ser))
572 SER_UART2_BUS_TXINIT;
577 static void uart2_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
582 static void uart2_enabletxirq(struct SerialHardware *_hw)
584 struct AvrSerial *hw = (struct AvrSerial *)_hw;
587 * WARNING: racy code here! The tx interrupt
588 * sets hw->sending to false when it runs with
589 * an empty fifo. The order of the statements
590 * in the if-block matters.
595 SER_UART2_BUS_TXBEGIN;
599 static void uart2_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
601 /* Compute baud-rate period */
602 uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1;
604 UBRR2H = (period) >> 8;
607 //DB(kprintf("uart2_setbaudrate(rate=%ld): period=%d\n", rate, period);)
610 static void uart2_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
612 UCSR2C = (UCSR2C & ~(BV(UPM21) | BV(UPM20))) | ((parity) << UPM20);
615 #endif // AVR_HAS_UART2
619 static void uart3_init(
620 UNUSED_ARG(struct SerialHardware *, _hw),
621 UNUSED_ARG(struct Serial *, ser))
623 SER_UART3_BUS_TXINIT;
628 static void uart3_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
633 static void uart3_enabletxirq(struct SerialHardware *_hw)
635 struct AvrSerial *hw = (struct AvrSerial *)_hw;
638 * WARNING: racy code here! The tx interrupt
639 * sets hw->sending to false when it runs with
640 * an empty fifo. The order of the statements
641 * in the if-block matters.
646 SER_UART3_BUS_TXBEGIN;
650 static void uart3_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
652 /* Compute baud-rate period */
653 uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1;
655 UBRR3H = (period) >> 8;
658 //DB(kprintf("uart3_setbaudrate(rate=%ld): period=%d\n", rate, period);)
661 static void uart3_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
663 UCSR3C = (UCSR3C & ~(BV(UPM31) | BV(UPM30))) | ((parity) << UPM30);
666 #endif // AVR_HAS_UART3
669 static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
672 * Set MOSI and SCK ports out, MISO in.
674 * The ATmega64/128 datasheet explicitly states that the input/output
675 * state of the SPI pins is not significant, as when the SPI is
676 * active the I/O port are overrided.
677 * This is *blatantly FALSE*.
679 * Moreover, the MISO pin on the board_kc *must* be in high impedance
680 * state even when the SPI is off, because the line is wired together
681 * with the KBus serial RX, and the transmitter of the slave boards
682 * would be unable to drive the line.
684 ATOMIC(SPI_DDR |= (BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT)));
687 * If the SPI master mode is activated and the SS pin is in input and tied low,
688 * the SPI hardware will automatically switch to slave mode!
689 * For proper communication this pins should therefore be:
691 * - as input but tied high forever!
692 * This driver set the pin as output.
694 #warning FIXME:SPI SS pin set as output for proper operation, check schematics for possible conflicts.
695 ATOMIC(SPI_DDR |= BV(SPI_SS_BIT));
697 ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT));
698 /* Enable SPI, IRQ on, Master */
699 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR);
702 #if CONFIG_SPI_DATA_ORDER == SER_LSB_FIRST
706 /* Set SPI clock rate */
707 #if CONFIG_SPI_CLOCK_DIV == 128
708 SPCR |= (BV(SPR1) | BV(SPR0));
709 #elif (CONFIG_SPI_CLOCK_DIV == 64 || CONFIG_SPI_CLOCK_DIV == 32)
711 #elif (CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 8)
713 #elif (CONFIG_SPI_CLOCK_DIV == 4 || CONFIG_SPI_CLOCK_DIV == 2)
714 // SPR0 & SDPR1 both at 0
716 #error Unsupported SPI clock division factor.
719 /* Set SPI2X bit (spi double frequency) */
720 #if (CONFIG_SPI_CLOCK_DIV == 128 || CONFIG_SPI_CLOCK_DIV == 64 \
721 || CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 4)
723 #elif (CONFIG_SPI_CLOCK_DIV == 32 || CONFIG_SPI_CLOCK_DIV == 8 || CONFIG_SPI_CLOCK_DIV == 2)
726 #error Unsupported SPI clock division factor.
729 /* Set clock polarity */
730 #if CONFIG_SPI_CLOCK_POL == 1
734 /* Set clock phase */
735 #if CONFIG_SPI_CLOCK_PHASE == 1
743 static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
749 /* Set all pins as inputs */
750 ATOMIC(SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT) | BV(SPI_SS_BIT)));
753 static void spi_starttx(struct SerialHardware *_hw)
755 struct AvrSerial *hw = (struct AvrSerial *)_hw;
758 IRQ_SAVE_DISABLE(flags);
760 /* Send data only if the SPI is not already transmitting */
761 if (!hw->sending && !fifo_isempty(&ser_handles[SER_SPI]->txfifo))
764 SPDR = fifo_pop(&ser_handles[SER_SPI]->txfifo);
770 static void spi_setbaudrate(
771 UNUSED_ARG(struct SerialHardware *, _hw),
772 UNUSED_ARG(unsigned long, rate))
777 static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
782 static bool tx_sending(struct SerialHardware* _hw)
784 struct AvrSerial *hw = (struct AvrSerial *)_hw;
790 // FIXME: move into compiler.h? Ditch?
792 #define C99INIT(name,val) .name = val
793 #elif defined(__GNUC__)
794 #define C99INIT(name,val) name: val
796 #warning No designated initializers, double check your code
797 #define C99INIT(name,val) (val)
801 * High-level interface data structures
803 static const struct SerialHardwareVT UART0_VT =
805 C99INIT(init, uart0_init),
806 C99INIT(cleanup, uart0_cleanup),
807 C99INIT(setBaudrate, uart0_setbaudrate),
808 C99INIT(setParity, uart0_setparity),
809 C99INIT(txStart, uart0_enabletxirq),
810 C99INIT(txSending, tx_sending),
814 static const struct SerialHardwareVT UART1_VT =
816 C99INIT(init, uart1_init),
817 C99INIT(cleanup, uart1_cleanup),
818 C99INIT(setBaudrate, uart1_setbaudrate),
819 C99INIT(setParity, uart1_setparity),
820 C99INIT(txStart, uart1_enabletxirq),
821 C99INIT(txSending, tx_sending),
823 #endif // AVR_HAS_UART1
826 static const struct SerialHardwareVT UART2_VT =
828 C99INIT(init, uart2_init),
829 C99INIT(cleanup, uart2_cleanup),
830 C99INIT(setBaudrate, uart2_setbaudrate),
831 C99INIT(setParity, uart2_setparity),
832 C99INIT(txStart, uart2_enabletxirq),
833 C99INIT(txSending, tx_sending),
835 #endif // AVR_HAS_UART2
838 static const struct SerialHardwareVT UART3_VT =
840 C99INIT(init, uart3_init),
841 C99INIT(cleanup, uart3_cleanup),
842 C99INIT(setBaudrate, uart3_setbaudrate),
843 C99INIT(setParity, uart3_setparity),
844 C99INIT(txStart, uart3_enabletxirq),
845 C99INIT(txSending, tx_sending),
847 #endif // AVR_HAS_UART3
849 static const struct SerialHardwareVT SPI_VT =
851 C99INIT(init, spi_init),
852 C99INIT(cleanup, spi_cleanup),
853 C99INIT(setBaudrate, spi_setbaudrate),
854 C99INIT(setParity, spi_setparity),
855 C99INIT(txStart, spi_starttx),
856 C99INIT(txSending, tx_sending),
859 static struct AvrSerial UARTDescs[SER_CNT] =
863 C99INIT(table, &UART0_VT),
864 C99INIT(txbuffer, uart0_txbuffer),
865 C99INIT(rxbuffer, uart0_rxbuffer),
866 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
867 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
869 C99INIT(sending, false),
874 C99INIT(table, &UART1_VT),
875 C99INIT(txbuffer, uart1_txbuffer),
876 C99INIT(rxbuffer, uart1_rxbuffer),
877 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
878 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
880 C99INIT(sending, false),
886 C99INIT(table, &UART2_VT),
887 C99INIT(txbuffer, uart2_txbuffer),
888 C99INIT(rxbuffer, uart2_rxbuffer),
889 C99INIT(txbuffer_size, sizeof(uart2_txbuffer)),
890 C99INIT(rxbuffer_size, sizeof(uart2_rxbuffer)),
892 C99INIT(sending, false),
898 C99INIT(table, &UART3_VT),
899 C99INIT(txbuffer, uart3_txbuffer),
900 C99INIT(rxbuffer, uart3_rxbuffer),
901 C99INIT(txbuffer_size, sizeof(uart3_txbuffer)),
902 C99INIT(rxbuffer_size, sizeof(uart3_rxbuffer)),
904 C99INIT(sending, false),
909 C99INIT(table, &SPI_VT),
910 C99INIT(txbuffer, spi_txbuffer),
911 C99INIT(rxbuffer, spi_rxbuffer),
912 C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
913 C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
915 C99INIT(sending, false),
919 struct SerialHardware *ser_hw_getdesc(int unit)
921 ASSERT(unit < SER_CNT);
922 return &UARTDescs[unit].hw;
930 #if CONFIG_SER_HWHANDSHAKE
932 /// This interrupt is triggered when the CTS line goes high
935 // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
936 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
937 EIMSK &= ~EIMSKF_CTS;
940 #endif // CONFIG_SER_HWHANDSHAKE
944 * Serial 0 TX interrupt handler
946 DECLARE_ISR(USART0_UDRE_vect)
950 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART0]->txfifo;
952 if (fifo_isempty(txfifo))
955 #ifndef SER_UART0_BUS_TXOFF
956 UARTDescs[SER_UART0].sending = false;
959 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
962 // Disable rx interrupt and tx, enable CTS interrupt
964 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
971 char c = fifo_pop(txfifo);
972 SER_UART0_BUS_TXCHAR(c);
978 #ifdef SER_UART0_BUS_TXOFF
980 * Serial port 0 TX complete interrupt handler.
982 * This IRQ is usually disabled. The UDR-empty interrupt
983 * enables it when there's no more data to transmit.
984 * We need to wait until the last character has been
985 * transmitted before switching the 485 transceiver to
988 * The txfifo might have been refilled by putchar() while
989 * we were waiting for the transmission complete interrupt.
990 * In this case, we must restart the UDR empty interrupt,
991 * otherwise we'd stop the serial port with some data
992 * still pending in the buffer.
994 DECLARE_ISR(USART0_TX_vect)
998 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART0]->txfifo;
999 if (fifo_isempty(txfifo))
1001 SER_UART0_BUS_TXOFF;
1002 UARTDescs[SER_UART0].sending = false;
1005 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
1009 #endif /* SER_UART0_BUS_TXOFF */
1015 * Serial 1 TX interrupt handler
1017 DECLARE_ISR(USART1_UDRE_vect)
1021 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART1]->txfifo;
1023 if (fifo_isempty(txfifo))
1025 SER_UART1_BUS_TXEND;
1026 #ifndef SER_UART1_BUS_TXOFF
1027 UARTDescs[SER_UART1].sending = false;
1030 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
1031 else if (!IS_CTS_ON)
1033 // Disable rx interrupt and tx, enable CTS interrupt
1035 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
1037 EIMSK |= EIMSKF_CTS;
1042 char c = fifo_pop(txfifo);
1043 SER_UART1_BUS_TXCHAR(c);
1049 #ifdef SER_UART1_BUS_TXOFF
1051 * Serial port 1 TX complete interrupt handler.
1053 * \sa port 0 TX complete handler.
1055 DECLARE_ISR(USART1_TX_vect)
1059 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART1]->txfifo;
1060 if (fifo_isempty(txfifo))
1062 SER_UART1_BUS_TXOFF;
1063 UARTDescs[SER_UART1].sending = false;
1066 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
1070 #endif /* SER_UART1_BUS_TXOFF */
1072 #endif // AVR_HAS_UART1
1077 * Serial 2 TX interrupt handler
1079 DECLARE_ISR(USART2_UDRE_vect)
1083 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART2]->txfifo;
1085 if (fifo_isempty(txfifo))
1087 SER_UART2_BUS_TXEND;
1088 #ifndef SER_UART2_BUS_TXOFF
1089 UARTDescs[SER_UART2].sending = false;
1094 char c = fifo_pop(txfifo);
1095 SER_UART2_BUS_TXCHAR(c);
1101 #ifdef SER_UART2_BUS_TXOFF
1103 * Serial port 2 TX complete interrupt handler.
1105 * \sa port 0 TX complete handler.
1107 DECLARE_ISR(USART2_TX_vect)
1111 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART2]->txfifo;
1112 if (fifo_isempty(txfifo))
1114 SER_UART2_BUS_TXOFF;
1115 UARTDescs[SER_UART2].sending = false;
1118 UCSR2B = BV(BIT_RXCIE2) | BV(BIT_UDRIE2) | BV(BIT_RXEN2) | BV(BIT_TXEN2);
1122 #endif /* SER_UART2_BUS_TXOFF */
1124 #endif // AVR_HAS_UART2
1129 * Serial 3 TX interrupt handler
1131 DECLARE_ISR(USART3_UDRE_vect)
1135 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART3]->txfifo;
1137 if (fifo_isempty(txfifo))
1139 SER_UART3_BUS_TXEND;
1140 #ifndef SER_UART3_BUS_TXOFF
1141 UARTDescs[SER_UART3].sending = false;
1146 char c = fifo_pop(txfifo);
1147 SER_UART3_BUS_TXCHAR(c);
1153 #ifdef SER_UART3_BUS_TXOFF
1155 * Serial port 3 TX complete interrupt handler.
1157 * \sa port 0 TX complete handler.
1159 DECLARE_ISR(USART3_TX_vect)
1163 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART3]->txfifo;
1164 if (fifo_isempty(txfifo))
1166 SER_UART3_BUS_TXOFF;
1167 UARTDescs[SER_UART3].sending = false;
1170 UCSR3B = BV(BIT_RXCIE3) | BV(BIT_UDRIE3) | BV(BIT_RXEN3) | BV(BIT_TXEN3);
1174 #endif /* SER_UART3_BUS_TXOFF */
1176 #endif // AVR_HAS_UART3
1180 * Serial 0 RX complete interrupt handler.
1182 * This handler is interruptible.
1183 * Interrupt are reenabled as soon as recv complete interrupt is
1184 * disabled. Using INTERRUPT() is troublesome when the serial
1185 * is heavily loaded, because an interrupt could be retriggered
1186 * when executing the handler prologue before RXCIE is disabled.
1188 * \note The code that re-enables interrupts is commented out
1189 * because in some nasty cases the interrupt is retriggered.
1190 * This is probably due to the RXC flag being set before
1191 * RXCIE is cleared. Unfortunately the RXC flag is read-only
1192 * and can't be cleared by code.
1194 DECLARE_ISR(USART0_RX_vect)
1198 /* Disable Recv complete IRQ */
1199 //UCSR0B &= ~BV(RXCIE);
1202 /* Should be read before UDR */
1203 ser_handles[SER_UART0]->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
1205 /* To clear the RXC flag we must _always_ read the UDR even when we're
1206 * not going to accept the incoming data, otherwise a new interrupt
1207 * will occur once the handler terminates.
1210 struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART0]->rxfifo;
1212 if (fifo_isfull(rxfifo))
1213 ser_handles[SER_UART0]->status |= SERRF_RXFIFOOVERRUN;
1216 fifo_push(rxfifo, c);
1217 #if CONFIG_SER_HWHANDSHAKE
1218 if (fifo_isfull(rxfifo))
1223 /* Reenable receive complete int */
1225 //UCSR0B |= BV(RXCIE);
1234 * Serial 1 RX complete interrupt handler.
1236 * This handler is interruptible.
1237 * Interrupt are reenabled as soon as recv complete interrupt is
1238 * disabled. Using INTERRUPT() is troublesome when the serial
1239 * is heavily loaded, because an interrupt could be retriggered
1240 * when executing the handler prologue before RXCIE is disabled.
1242 * \see DECLARE_ISR(USART1_RX_vect)
1244 DECLARE_ISR(USART1_RX_vect)
1248 /* Disable Recv complete IRQ */
1249 //UCSR1B &= ~BV(RXCIE);
1252 /* Should be read before UDR */
1253 ser_handles[SER_UART1]->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
1255 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
1256 * not going to accept the incoming data
1259 struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART1]->rxfifo;
1260 //ASSERT_VALID_FIFO(rxfifo);
1262 if (UNLIKELY(fifo_isfull(rxfifo)))
1263 ser_handles[SER_UART1]->status |= SERRF_RXFIFOOVERRUN;
1266 fifo_push(rxfifo, c);
1267 #if CONFIG_SER_HWHANDSHAKE
1268 if (fifo_isfull(rxfifo))
1272 /* Re-enable receive complete int */
1274 //UCSR1B |= BV(RXCIE);
1279 #endif // AVR_HAS_UART1
1284 * Serial 2 RX complete interrupt handler.
1286 * This handler is interruptible.
1287 * Interrupt are reenabled as soon as recv complete interrupt is
1288 * disabled. Using INTERRUPT() is troublesome when the serial
1289 * is heavily loaded, because an interrupt could be retriggered
1290 * when executing the handler prologue before RXCIE is disabled.
1292 * \see DECLARE_ISR(USART2_RX_vect)
1294 DECLARE_ISR(USART2_RX_vect)
1298 /* Disable Recv complete IRQ */
1299 //UCSR1B &= ~BV(RXCIE);
1302 /* Should be read before UDR */
1303 ser_handles[SER_UART2]->status |= UCSR2A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
1305 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
1306 * not going to accept the incoming data
1309 struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART2]->rxfifo;
1310 //ASSERT_VALID_FIFO(rxfifo);
1312 if (UNLIKELY(fifo_isfull(rxfifo)))
1313 ser_handles[SER_UART2]->status |= SERRF_RXFIFOOVERRUN;
1316 fifo_push(rxfifo, c);
1317 #if CONFIG_SER_HWHANDSHAKE
1318 if (fifo_isfull(rxfifo))
1322 /* Re-enable receive complete int */
1324 //UCSR1B |= BV(RXCIE);
1329 #endif // AVR_HAS_UART2
1334 * Serial 3 RX complete interrupt handler.
1336 * This handler is interruptible.
1337 * Interrupt are reenabled as soon as recv complete interrupt is
1338 * disabled. Using INTERRUPT() is troublesome when the serial
1339 * is heavily loaded, because an interrupt could be retriggered
1340 * when executing the handler prologue before RXCIE is disabled.
1342 * \see DECLARE_ISR(USART3_RX_vect)
1344 DECLARE_ISR(USART3_RX_vect)
1348 /* Disable Recv complete IRQ */
1349 //UCSR1B &= ~BV(RXCIE);
1352 /* Should be read before UDR */
1353 ser_handles[SER_UART3]->status |= UCSR3A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
1355 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
1356 * not going to accept the incoming data
1359 struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART3]->rxfifo;
1360 //ASSERT_VALID_FIFO(rxfifo);
1362 if (UNLIKELY(fifo_isfull(rxfifo)))
1363 ser_handles[SER_UART3]->status |= SERRF_RXFIFOOVERRUN;
1366 fifo_push(rxfifo, c);
1367 #if CONFIG_SER_HWHANDSHAKE
1368 if (fifo_isfull(rxfifo))
1372 /* Re-enable receive complete int */
1374 //UCSR1B |= BV(RXCIE);
1379 #endif // AVR_HAS_UART3
1383 * SPI interrupt handler
1385 DECLARE_ISR(SPI_STC_vect)
1389 /* Read incoming byte. */
1390 if (!fifo_isfull(&ser_handles[SER_SPI]->rxfifo))
1391 fifo_push(&ser_handles[SER_SPI]->rxfifo, SPDR);
1395 ser_handles[SER_SPI]->status |= SERRF_RXFIFOOVERRUN;
1399 if (!fifo_isempty(&ser_handles[SER_SPI]->txfifo))
1400 SPDR = fifo_pop(&ser_handles[SER_SPI]->txfifo);
1402 UARTDescs[SER_SPI].sending = false;