4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2003, 2004 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2000 Bernie Innocenti <bernie@codewiz.org>
34 * \brief AVR UART and SPI I/O driver (Implementation)
38 * \author Bernie Innocenti <bernie@codewiz.org>
39 * \author Stefano Fedrigo <aleph@develer.com>
42 #include "hw/hw_ser.h" /* Required for bus macros overrides */
43 #include <hw/hw_cpufreq.h> /* CPU_FREQ */
45 #include "cfg/cfg_ser.h"
47 #include <cfg/macros.h> /* DIV_ROUND */
48 #include <cfg/debug.h>
51 #include <drv/ser_p.h>
52 #include <drv/timer.h>
54 #include <struct/fifobuf.h>
58 #if defined(__AVR_LIBC_VERSION__) && (__AVR_LIBC_VERSION__ >= 10400UL)
59 #include <avr/interrupt.h>
61 #include <avr/signal.h>
65 #if !CONFIG_SER_HWHANDSHAKE
67 * \name Hardware handshake (RTS/CTS).
70 #define RTS_ON do {} while (0)
71 #define RTS_OFF do {} while (0)
72 #define IS_CTS_ON true
73 #define EIMSKF_CTS 0 /**< Dummy value, must be overridden */
77 #if CPU_AVR_ATMEGA1281
78 #define BIT_RXCIE0 RXCIE0
79 #define BIT_RXEN0 RXEN0
80 #define BIT_TXEN0 TXEN0
81 #define BIT_UDRIE0 UDRIE0
83 #define BIT_RXCIE1 RXCIE1
84 #define BIT_RXEN1 RXEN1
85 #define BIT_TXEN1 TXEN1
86 #define BIT_UDRIE1 UDRIE1
88 #define BIT_RXCIE0 RXCIE
89 #define BIT_RXEN0 RXEN
90 #define BIT_TXEN0 TXEN
91 #define BIT_UDRIE0 UDRIE
93 #define BIT_RXCIE1 RXCIE
94 #define BIT_RXEN1 RXEN
95 #define BIT_TXEN1 TXEN
96 #define BIT_UDRIE1 UDRIE
101 * \name Overridable serial bus hooks
103 * These can be redefined in hw.h to implement
104 * special bus policies such as half-duplex, 485, etc.
108 * TXBEGIN TXCHAR TXEND TXOFF
109 * | __________|__________ | |
112 * ______ __ __ __ __ __ __ ________________
113 * \/ \/ \/ \/ \/ \/ \/
114 * ______/\__/\__/\__/\__/\__/\__/
120 #ifndef SER_UART0_BUS_TXINIT
122 * Default TXINIT macro - invoked in uart0_init()
124 * - Enable both the receiver and the transmitter
125 * - Enable only the RX complete interrupt
127 #define SER_UART0_BUS_TXINIT do { \
128 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
132 #ifndef SER_UART0_BUS_TXBEGIN
134 * Invoked before starting a transmission
136 * - Enable both the receiver and the transmitter
137 * - Enable both the RX complete and UDR empty interrupts
139 #define SER_UART0_BUS_TXBEGIN do { \
140 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
144 #ifndef SER_UART0_BUS_TXCHAR
146 * Invoked to send one character.
148 #define SER_UART0_BUS_TXCHAR(c) do { \
153 #ifndef SER_UART0_BUS_TXEND
155 * Invoked as soon as the txfifo becomes empty
157 * - Keep both the receiver and the transmitter enabled
158 * - Keep the RX complete interrupt enabled
159 * - Disable the UDR empty interrupt
161 #define SER_UART0_BUS_TXEND do { \
162 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
166 #ifndef SER_UART0_BUS_TXOFF
168 * \def SER_UART0_BUS_TXOFF
170 * Invoked after the last character has been transmitted
172 * The default is no action.
175 #define SER_UART0_BUS_TXOFF
179 #ifndef SER_UART1_BUS_TXINIT
180 /** \sa SER_UART0_BUS_TXINIT */
181 #define SER_UART1_BUS_TXINIT do { \
182 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
185 #ifndef SER_UART1_BUS_TXBEGIN
186 /** \sa SER_UART0_BUS_TXBEGIN */
187 #define SER_UART1_BUS_TXBEGIN do { \
188 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
191 #ifndef SER_UART1_BUS_TXCHAR
192 /** \sa SER_UART0_BUS_TXCHAR */
193 #define SER_UART1_BUS_TXCHAR(c) do { \
197 #ifndef SER_UART1_BUS_TXEND
198 /** \sa SER_UART0_BUS_TXEND */
199 #define SER_UART1_BUS_TXEND do { \
200 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
203 #ifndef SER_UART1_BUS_TXOFF
205 * \def SER_UART1_BUS_TXOFF
207 * \see SER_UART0_BUS_TXOFF
210 #define SER_UART1_BUS_TXOFF
217 * \name Overridable SPI hooks
219 * These can be redefined in hw.h to implement
220 * special bus policies such as slave select pin handling, etc.
224 #ifndef SER_SPI_BUS_TXINIT
226 * Default TXINIT macro - invoked in spi_init()
227 * The default is no action.
229 #define SER_SPI_BUS_TXINIT
232 #ifndef SER_SPI_BUS_TXCLOSE
234 * Invoked after the last character has been transmitted.
235 * The default is no action.
237 #define SER_SPI_BUS_TXCLOSE
242 /* SPI port and pin configuration */
243 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 || CPU_AVR_ATMEGA1281
244 #define SPI_PORT PORTB
246 #define SPI_SS_BIT PB0
247 #define SPI_SCK_BIT PB1
248 #define SPI_MOSI_BIT PB2
249 #define SPI_MISO_BIT PB3
250 #elif CPU_AVR_ATMEGA8
251 #define SPI_PORT PORTB
253 #define SPI_SS_BIT PB2
254 #define SPI_SCK_BIT PB5
255 #define SPI_MOSI_BIT PB3
256 #define SPI_MISO_BIT PB4
258 #error Unknown architecture
261 /* USART register definitions */
262 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
263 #define AVR_HAS_UART1 1
264 #elif CPU_AVR_ATMEGA8
265 #define AVR_HAS_UART1 0
272 #define SIG_UART0_DATA SIG_UART_DATA
273 #define SIG_UART0_RECV SIG_UART_RECV
274 #define SIG_UART0_TRANS SIG_UART_TRANS
275 #elif CPU_AVR_ATMEGA103
276 #define AVR_HAS_UART1 0
281 #define SIG_UART0_DATA SIG_UART_DATA
282 #define SIG_UART0_RECV SIG_UART_RECV
283 #define SIG_UART0_TRANS SIG_UART_TRANS
285 #error Unknown architecture
289 /* From the high-level serial driver */
290 extern struct Serial *ser_handles[SER_CNT];
292 /* TX and RX buffers */
293 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
294 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
296 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
297 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
299 static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
300 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
304 * Internal hardware state structure
306 * The \a sending variable is true while the transmission
307 * interrupt is retriggering itself.
309 * For the USARTs the \a sending flag is useful for taking specific
310 * actions before sending a burst of data, at the start of a trasmission
311 * but not before every char sent.
313 * For the SPI, this flag is necessary because the SPI sends and receives
314 * bytes at the same time and the SPI IRQ is unique for send/receive.
315 * The only way to start transmission is to write data in SPDR (this
316 * is done by spi_starttx()). We do this *only* if a transfer is
317 * not already started.
321 struct SerialHardware hw;
322 volatile bool sending;
330 static void uart0_init(
331 UNUSED_ARG(struct SerialHardware *, _hw),
332 UNUSED_ARG(struct Serial *, ser))
334 SER_UART0_BUS_TXINIT;
339 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
344 static void uart0_enabletxirq(struct SerialHardware *_hw)
346 struct AvrSerial *hw = (struct AvrSerial *)_hw;
349 * WARNING: racy code here! The tx interrupt sets hw->sending to false
350 * when it runs with an empty fifo. The order of statements in the
356 SER_UART0_BUS_TXBEGIN;
360 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
362 /* Compute baud-rate period */
363 uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1;
365 #if !CPU_AVR_ATMEGA103
366 UBRR0H = (period) >> 8;
370 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
373 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
375 #if !CPU_AVR_ATMEGA103
376 UCSR0C = (UCSR0C & ~(BV(UPM01) | BV(UPM00))) | ((parity) << UPM00);
382 static void uart1_init(
383 UNUSED_ARG(struct SerialHardware *, _hw),
384 UNUSED_ARG(struct Serial *, ser))
386 SER_UART1_BUS_TXINIT;
391 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
396 static void uart1_enabletxirq(struct SerialHardware *_hw)
398 struct AvrSerial *hw = (struct AvrSerial *)_hw;
401 * WARNING: racy code here! The tx interrupt
402 * sets hw->sending to false when it runs with
403 * an empty fifo. The order of the statements
404 * in the if-block matters.
409 SER_UART1_BUS_TXBEGIN;
413 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
415 /* Compute baud-rate period */
416 uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1;
418 UBRR1H = (period) >> 8;
421 //DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
424 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
426 UCSR1C = (UCSR1C & ~(BV(UPM11) | BV(UPM10))) | ((parity) << UPM10);
429 #endif // AVR_HAS_UART1
431 static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
434 * Set MOSI and SCK ports out, MISO in.
436 * The ATmega64/128 datasheet explicitly states that the input/output
437 * state of the SPI pins is not significant, as when the SPI is
438 * active the I/O port are overrided.
439 * This is *blatantly FALSE*.
441 * Moreover, the MISO pin on the board_kc *must* be in high impedance
442 * state even when the SPI is off, because the line is wired together
443 * with the KBus serial RX, and the transmitter of the slave boards
444 * would be unable to drive the line.
446 ATOMIC(SPI_DDR |= (BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT)));
449 * If the SPI master mode is activated and the SS pin is in input and tied low,
450 * the SPI hardware will automatically switch to slave mode!
451 * For proper communication this pins should therefore be:
453 * - as input but tied high forever!
454 * This driver set the pin as output.
456 #warning SPI SS pin set as output for proper operation, check schematics for possible conflicts.
457 ATOMIC(SPI_DDR |= BV(SPI_SS_BIT));
459 ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT));
460 /* Enable SPI, IRQ on, Master */
461 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR);
464 #if CONFIG_SPI_DATA_ORDER == SER_LSB_FIRST
468 /* Set SPI clock rate */
469 #if CONFIG_SPI_CLOCK_DIV == 128
470 SPCR |= (BV(SPR1) | BV(SPR0));
471 #elif (CONFIG_SPI_CLOCK_DIV == 64 || CONFIG_SPI_CLOCK_DIV == 32)
473 #elif (CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 8)
475 #elif (CONFIG_SPI_CLOCK_DIV == 4 || CONFIG_SPI_CLOCK_DIV == 2)
476 // SPR0 & SDPR1 both at 0
478 #error Unsupported SPI clock division factor.
481 /* Set SPI2X bit (spi double frequency) */
482 #if (CONFIG_SPI_CLOCK_DIV == 128 || CONFIG_SPI_CLOCK_DIV == 64 \
483 || CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 4)
485 #elif (CONFIG_SPI_CLOCK_DIV == 32 || CONFIG_SPI_CLOCK_DIV == 8 || CONFIG_SPI_CLOCK_DIV == 2)
488 #error Unsupported SPI clock division factor.
491 /* Set clock polarity */
492 #if CONFIG_SPI_CLOCK_POL == 1
496 /* Set clock phase */
497 #if CONFIG_SPI_CLOCK_PHASE == 1
505 static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
511 /* Set all pins as inputs */
512 ATOMIC(SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT) | BV(SPI_SS_BIT)));
515 static void spi_starttx(struct SerialHardware *_hw)
517 struct AvrSerial *hw = (struct AvrSerial *)_hw;
520 IRQ_SAVE_DISABLE(flags);
522 /* Send data only if the SPI is not already transmitting */
523 if (!hw->sending && !fifo_isempty(&ser_handles[SER_SPI]->txfifo))
526 SPDR = fifo_pop(&ser_handles[SER_SPI]->txfifo);
532 static void spi_setbaudrate(
533 UNUSED_ARG(struct SerialHardware *, _hw),
534 UNUSED_ARG(unsigned long, rate))
539 static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
544 static bool tx_sending(struct SerialHardware* _hw)
546 struct AvrSerial *hw = (struct AvrSerial *)_hw;
552 // FIXME: move into compiler.h? Ditch?
554 #define C99INIT(name,val) .name = val
555 #elif defined(__GNUC__)
556 #define C99INIT(name,val) name: val
558 #warning No designated initializers, double check your code
559 #define C99INIT(name,val) (val)
563 * High-level interface data structures
565 static const struct SerialHardwareVT UART0_VT =
567 C99INIT(init, uart0_init),
568 C99INIT(cleanup, uart0_cleanup),
569 C99INIT(setBaudrate, uart0_setbaudrate),
570 C99INIT(setParity, uart0_setparity),
571 C99INIT(txStart, uart0_enabletxirq),
572 C99INIT(txSending, tx_sending),
576 static const struct SerialHardwareVT UART1_VT =
578 C99INIT(init, uart1_init),
579 C99INIT(cleanup, uart1_cleanup),
580 C99INIT(setBaudrate, uart1_setbaudrate),
581 C99INIT(setParity, uart1_setparity),
582 C99INIT(txStart, uart1_enabletxirq),
583 C99INIT(txSending, tx_sending),
585 #endif // AVR_HAS_UART1
587 static const struct SerialHardwareVT SPI_VT =
589 C99INIT(init, spi_init),
590 C99INIT(cleanup, spi_cleanup),
591 C99INIT(setBaudrate, spi_setbaudrate),
592 C99INIT(setParity, spi_setparity),
593 C99INIT(txStart, spi_starttx),
594 C99INIT(txSending, tx_sending),
597 static struct AvrSerial UARTDescs[SER_CNT] =
601 C99INIT(table, &UART0_VT),
602 C99INIT(txbuffer, uart0_txbuffer),
603 C99INIT(rxbuffer, uart0_rxbuffer),
604 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
605 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
607 C99INIT(sending, false),
612 C99INIT(table, &UART1_VT),
613 C99INIT(txbuffer, uart1_txbuffer),
614 C99INIT(rxbuffer, uart1_rxbuffer),
615 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
616 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
618 C99INIT(sending, false),
623 C99INIT(table, &SPI_VT),
624 C99INIT(txbuffer, spi_txbuffer),
625 C99INIT(rxbuffer, spi_rxbuffer),
626 C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
627 C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
629 C99INIT(sending, false),
633 struct SerialHardware *ser_hw_getdesc(int unit)
635 ASSERT(unit < SER_CNT);
636 return &UARTDescs[unit].hw;
644 #if CONFIG_SER_HWHANDSHAKE
646 /// This interrupt is triggered when the CTS line goes high
649 // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
650 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
651 EIMSK &= ~EIMSKF_CTS;
654 #endif // CONFIG_SER_HWHANDSHAKE
658 * Serial 0 TX interrupt handler
660 SIGNAL(USART0_UDRE_vect)
664 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART0]->txfifo;
666 if (fifo_isempty(txfifo))
669 #ifndef SER_UART0_BUS_TXOFF
670 UARTDescs[SER_UART0].sending = false;
673 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
676 // Disable rx interrupt and tx, enable CTS interrupt
678 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
685 char c = fifo_pop(txfifo);
686 SER_UART0_BUS_TXCHAR(c);
692 #ifdef SER_UART0_BUS_TXOFF
694 * Serial port 0 TX complete interrupt handler.
696 * This IRQ is usually disabled. The UDR-empty interrupt
697 * enables it when there's no more data to transmit.
698 * We need to wait until the last character has been
699 * transmitted before switching the 485 transceiver to
702 * The txfifo might have been refilled by putchar() while
703 * we were waiting for the transmission complete interrupt.
704 * In this case, we must restart the UDR empty interrupt,
705 * otherwise we'd stop the serial port with some data
706 * still pending in the buffer.
708 SIGNAL(SIG_UART0_TRANS)
712 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART0]->txfifo;
713 if (fifo_isempty(txfifo))
716 UARTDescs[SER_UART0].sending = false;
719 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
723 #endif /* SER_UART0_BUS_TXOFF */
729 * Serial 1 TX interrupt handler
731 SIGNAL(USART1_UDRE_vect)
735 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART1]->txfifo;
737 if (fifo_isempty(txfifo))
740 #ifndef SER_UART1_BUS_TXOFF
741 UARTDescs[SER_UART1].sending = false;
744 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
747 // Disable rx interrupt and tx, enable CTS interrupt
749 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
756 char c = fifo_pop(txfifo);
757 SER_UART1_BUS_TXCHAR(c);
763 #ifdef SER_UART1_BUS_TXOFF
765 * Serial port 1 TX complete interrupt handler.
767 * \sa port 0 TX complete handler.
769 SIGNAL(USART1_TX_vect)
773 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART1]->txfifo;
774 if (fifo_isempty(txfifo))
777 UARTDescs[SER_UART1].sending = false;
780 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
784 #endif /* SER_UART1_BUS_TXOFF */
786 #endif // AVR_HAS_UART1
790 * Serial 0 RX complete interrupt handler.
792 * This handler is interruptible.
793 * Interrupt are reenabled as soon as recv complete interrupt is
794 * disabled. Using INTERRUPT() is troublesome when the serial
795 * is heavily loaded, because an interrupt could be retriggered
796 * when executing the handler prologue before RXCIE is disabled.
798 * \note The code that re-enables interrupts is commented out
799 * because in some nasty cases the interrupt is retriggered.
800 * This is probably due to the RXC flag being set before
801 * RXCIE is cleared. Unfortunately the RXC flag is read-only
802 * and can't be cleared by code.
804 SIGNAL(USART0_RX_vect)
808 /* Disable Recv complete IRQ */
809 //UCSR0B &= ~BV(RXCIE);
812 /* Should be read before UDR */
813 ser_handles[SER_UART0]->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
815 /* To clear the RXC flag we must _always_ read the UDR even when we're
816 * not going to accept the incoming data, otherwise a new interrupt
817 * will occur once the handler terminates.
820 struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART0]->rxfifo;
822 if (fifo_isfull(rxfifo))
823 ser_handles[SER_UART0]->status |= SERRF_RXFIFOOVERRUN;
826 fifo_push(rxfifo, c);
827 #if CONFIG_SER_HWHANDSHAKE
828 if (fifo_isfull(rxfifo))
833 /* Reenable receive complete int */
835 //UCSR0B |= BV(RXCIE);
844 * Serial 1 RX complete interrupt handler.
846 * This handler is interruptible.
847 * Interrupt are reenabled as soon as recv complete interrupt is
848 * disabled. Using INTERRUPT() is troublesome when the serial
849 * is heavily loaded, because an interrupt could be retriggered
850 * when executing the handler prologue before RXCIE is disabled.
852 * \see SIGNAL(USART1_RX_vect)
854 SIGNAL(USART1_RX_vect)
858 /* Disable Recv complete IRQ */
859 //UCSR1B &= ~BV(RXCIE);
862 /* Should be read before UDR */
863 ser_handles[SER_UART1]->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
865 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
866 * not going to accept the incoming data
869 struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART1]->rxfifo;
870 //ASSERT_VALID_FIFO(rxfifo);
872 if (UNLIKELY(fifo_isfull(rxfifo)))
873 ser_handles[SER_UART1]->status |= SERRF_RXFIFOOVERRUN;
876 fifo_push(rxfifo, c);
877 #if CONFIG_SER_HWHANDSHAKE
878 if (fifo_isfull(rxfifo))
882 /* Re-enable receive complete int */
884 //UCSR1B |= BV(RXCIE);
889 #endif // AVR_HAS_UART1
893 * SPI interrupt handler
899 /* Read incoming byte. */
900 if (!fifo_isfull(&ser_handles[SER_SPI]->rxfifo))
901 fifo_push(&ser_handles[SER_SPI]->rxfifo, SPDR);
905 ser_handles[SER_SPI]->status |= SERRF_RXFIFOOVERRUN;
909 if (!fifo_isempty(&ser_handles[SER_SPI]->txfifo))
910 SPDR = fifo_pop(&ser_handles[SER_SPI]->txfifo);
912 UARTDescs[SER_SPI].sending = false;