4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2003, 2004, 2010 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2000 Bernie Innocenti <bernie@codewiz.org>
34 * \brief AVR UART and SPI I/O driver (Implementation)
36 * \author Bernie Innocenti <bernie@codewiz.org>
37 * \author Stefano Fedrigo <aleph@develer.com>
38 * \author Luca Ottaviano <lottaviano@develer.com>
41 #include "hw/hw_ser.h" /* Required for bus macros overrides */
42 #include <hw/hw_cpufreq.h> /* CPU_FREQ */
44 #include "cfg/cfg_ser.h"
46 #include <cfg/macros.h> /* DIV_ROUND */
47 #include <cfg/debug.h>
48 #include <cfg/cfg_arch.h> // ARCH_NIGHTTEST
51 #include <drv/ser_p.h>
52 #include <drv/timer.h>
54 #include <struct/fifobuf.h>
58 #if defined(__AVR_LIBC_VERSION__) && (__AVR_LIBC_VERSION__ >= 10400UL)
59 #include <avr/interrupt.h>
61 #include <avr/signal.h>
65 #if !CONFIG_SER_HWHANDSHAKE
67 * \name Hardware handshake (RTS/CTS).
70 #define RTS_ON do {} while (0)
71 #define RTS_OFF do {} while (0)
72 #define IS_CTS_ON true
73 #define EIMSKF_CTS 0 /**< Dummy value, must be overridden */
77 #if CPU_AVR_ATMEGA1281
78 #define BIT_RXCIE0 RXCIE0
79 #define BIT_RXEN0 RXEN0
80 #define BIT_TXEN0 TXEN0
81 #define BIT_UDRIE0 UDRIE0
83 #define BIT_RXCIE1 RXCIE1
84 #define BIT_RXEN1 RXEN1
85 #define BIT_TXEN1 TXEN1
86 #define BIT_UDRIE1 UDRIE1
87 #elif CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
88 #define BIT_RXCIE0 RXCIE0
89 #define BIT_RXEN0 RXEN0
90 #define BIT_TXEN0 TXEN0
91 #define BIT_UDRIE0 UDRIE0
93 #define BIT_RXCIE1 RXCIE0
94 #define BIT_RXEN1 RXEN0
95 #define BIT_TXEN1 TXEN0
96 #define BIT_UDRIE1 UDRIE0
98 #define BIT_RXCIE0 RXCIE
99 #define BIT_RXEN0 RXEN
100 #define BIT_TXEN0 TXEN
101 #define BIT_UDRIE0 UDRIE
103 #define BIT_RXCIE1 RXCIE
104 #define BIT_RXEN1 RXEN
105 #define BIT_TXEN1 TXEN
106 #define BIT_UDRIE1 UDRIE
111 * \name Overridable serial bus hooks
113 * These can be redefined in hw.h to implement
114 * special bus policies such as half-duplex, 485, etc.
118 * TXBEGIN TXCHAR TXEND TXOFF
119 * | __________|__________ | |
122 * ______ __ __ __ __ __ __ ________________
123 * \/ \/ \/ \/ \/ \/ \/
124 * ______/\__/\__/\__/\__/\__/\__/
130 #ifndef SER_UART0_BUS_TXINIT
132 * Default TXINIT macro - invoked in uart0_init()
134 * - Enable both the receiver and the transmitter
135 * - Enable only the RX complete interrupt
137 #define SER_UART0_BUS_TXINIT do { \
138 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
142 #ifndef SER_UART0_BUS_TXBEGIN
144 * Invoked before starting a transmission
146 * - Enable both the receiver and the transmitter
147 * - Enable both the RX complete and UDR empty interrupts
149 #define SER_UART0_BUS_TXBEGIN do { \
150 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
154 #ifndef SER_UART0_BUS_TXCHAR
156 * Invoked to send one character.
158 #define SER_UART0_BUS_TXCHAR(c) do { \
163 #ifndef SER_UART0_BUS_TXEND
165 * Invoked as soon as the txfifo becomes empty
167 * - Keep both the receiver and the transmitter enabled
168 * - Keep the RX complete interrupt enabled
169 * - Disable the UDR empty interrupt
171 #define SER_UART0_BUS_TXEND do { \
172 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
176 #ifndef SER_UART0_BUS_TXOFF
178 * \def SER_UART0_BUS_TXOFF
180 * Invoked after the last character has been transmitted
182 * The default is no action.
185 #define SER_UART0_BUS_TXOFF
189 #ifndef SER_UART1_BUS_TXINIT
190 /** \sa SER_UART0_BUS_TXINIT */
191 #define SER_UART1_BUS_TXINIT do { \
192 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
195 #ifndef SER_UART1_BUS_TXBEGIN
196 /** \sa SER_UART0_BUS_TXBEGIN */
197 #define SER_UART1_BUS_TXBEGIN do { \
198 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
201 #ifndef SER_UART1_BUS_TXCHAR
202 /** \sa SER_UART0_BUS_TXCHAR */
203 #define SER_UART1_BUS_TXCHAR(c) do { \
207 #ifndef SER_UART1_BUS_TXEND
208 /** \sa SER_UART0_BUS_TXEND */
209 #define SER_UART1_BUS_TXEND do { \
210 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
213 #ifndef SER_UART1_BUS_TXOFF
215 * \def SER_UART1_BUS_TXOFF
217 * \see SER_UART0_BUS_TXOFF
220 #define SER_UART1_BUS_TXOFF
227 * \name Overridable SPI hooks
229 * These can be redefined in hw.h to implement
230 * special bus policies such as slave select pin handling, etc.
234 #ifndef SER_SPI_BUS_TXINIT
236 * Default TXINIT macro - invoked in spi_init()
237 * The default is no action.
239 #define SER_SPI_BUS_TXINIT
242 #ifndef SER_SPI_BUS_TXCLOSE
244 * Invoked after the last character has been transmitted.
245 * The default is no action.
247 #define SER_SPI_BUS_TXCLOSE
252 /* SPI port and pin configuration */
253 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 || CPU_AVR_ATMEGA1281
254 #define SPI_PORT PORTB
256 #define SPI_SS_BIT PB0
257 #define SPI_SCK_BIT PB1
258 #define SPI_MOSI_BIT PB2
259 #define SPI_MISO_BIT PB3
260 // TODO: these bits are the same as ATMEGA8 but the defines in avr-gcc are different.
261 // They should be the same!
262 #elif CPU_AVR_ATMEGA328P
263 #define SPI_PORT PORTB
265 #define SPI_SS_BIT PORTB2
266 #define SPI_SCK_BIT PORTB5
267 #define SPI_MOSI_BIT PORTB3
268 #define SPI_MISO_BIT PORTB4
269 #elif CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA168
270 #define SPI_PORT PORTB
272 #define SPI_SS_BIT PB2
273 #define SPI_SCK_BIT PB5
274 #define SPI_MOSI_BIT PB3
275 #define SPI_MISO_BIT PB4
277 #error Unknown architecture
280 /* USART register definitions */
281 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
282 #define AVR_HAS_UART1 1
283 #elif CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
284 #define AVR_HAS_UART1 0
285 #define USART0_UDRE_vect USART_UDRE_vect
286 #define USART0_RX_vect USART_RX_vect
287 #define USART0_TX_vect USART_TX_vect
288 #elif CPU_AVR_ATMEGA8
289 #define AVR_HAS_UART1 0
296 #define USART0_UDRE_vect USART_UDRE_vect
297 #define USART0_RX_vect USART_RX_vect
298 #define USART0_TX_vect USART_TX_vect
299 #elif CPU_AVR_ATMEGA103
300 #define AVR_HAS_UART1 0
305 #define USART0_UDRE_vect USART_UDRE_vect
306 #define USART0_RX_vect USART_RX_vect
307 #define USART0_TX_vect USART_TX_vect
309 #error Unknown architecture
313 /* From the high-level serial driver */
314 extern struct Serial *ser_handles[SER_CNT];
316 /* TX and RX buffers */
317 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
318 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
320 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
321 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
323 static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
324 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
328 * Internal hardware state structure
330 * The \a sending variable is true while the transmission
331 * interrupt is retriggering itself.
333 * For the USARTs the \a sending flag is useful for taking specific
334 * actions before sending a burst of data, at the start of a trasmission
335 * but not before every char sent.
337 * For the SPI, this flag is necessary because the SPI sends and receives
338 * bytes at the same time and the SPI IRQ is unique for send/receive.
339 * The only way to start transmission is to write data in SPDR (this
340 * is done by spi_starttx()). We do this *only* if a transfer is
341 * not already started.
345 struct SerialHardware hw;
346 volatile bool sending;
354 static void uart0_init(
355 UNUSED_ARG(struct SerialHardware *, _hw),
356 UNUSED_ARG(struct Serial *, ser))
358 SER_UART0_BUS_TXINIT;
363 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
368 static void uart0_enabletxirq(struct SerialHardware *_hw)
370 struct AvrSerial *hw = (struct AvrSerial *)_hw;
373 * WARNING: racy code here! The tx interrupt sets hw->sending to false
374 * when it runs with an empty fifo. The order of statements in the
380 SER_UART0_BUS_TXBEGIN;
384 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
386 /* Compute baud-rate period */
387 uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1;
389 #if !CPU_AVR_ATMEGA103
390 UBRR0H = (period) >> 8;
394 //DB(kprintf("uart0_setbaudrate(rate=%lu): period=%d\n", rate, period);)
397 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
399 #if !CPU_AVR_ATMEGA103
400 UCSR0C = (UCSR0C & ~(BV(UPM01) | BV(UPM00))) | ((parity) << UPM00);
406 static void uart1_init(
407 UNUSED_ARG(struct SerialHardware *, _hw),
408 UNUSED_ARG(struct Serial *, ser))
410 SER_UART1_BUS_TXINIT;
415 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
420 static void uart1_enabletxirq(struct SerialHardware *_hw)
422 struct AvrSerial *hw = (struct AvrSerial *)_hw;
425 * WARNING: racy code here! The tx interrupt
426 * sets hw->sending to false when it runs with
427 * an empty fifo. The order of the statements
428 * in the if-block matters.
433 SER_UART1_BUS_TXBEGIN;
437 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
439 /* Compute baud-rate period */
440 uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, rate) - 1;
442 UBRR1H = (period) >> 8;
445 //DB(kprintf("uart1_setbaudrate(rate=%ld): period=%d\n", rate, period);)
448 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
450 UCSR1C = (UCSR1C & ~(BV(UPM11) | BV(UPM10))) | ((parity) << UPM10);
453 #endif // AVR_HAS_UART1
455 static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
458 * Set MOSI and SCK ports out, MISO in.
460 * The ATmega64/128 datasheet explicitly states that the input/output
461 * state of the SPI pins is not significant, as when the SPI is
462 * active the I/O port are overrided.
463 * This is *blatantly FALSE*.
465 * Moreover, the MISO pin on the board_kc *must* be in high impedance
466 * state even when the SPI is off, because the line is wired together
467 * with the KBus serial RX, and the transmitter of the slave boards
468 * would be unable to drive the line.
470 ATOMIC(SPI_DDR |= (BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT)));
473 * If the SPI master mode is activated and the SS pin is in input and tied low,
474 * the SPI hardware will automatically switch to slave mode!
475 * For proper communication this pins should therefore be:
477 * - as input but tied high forever!
478 * This driver set the pin as output.
480 #warning FIXME:SPI SS pin set as output for proper operation, check schematics for possible conflicts.
481 ATOMIC(SPI_DDR |= BV(SPI_SS_BIT));
483 ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT));
484 /* Enable SPI, IRQ on, Master */
485 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR);
488 #if CONFIG_SPI_DATA_ORDER == SER_LSB_FIRST
492 /* Set SPI clock rate */
493 #if CONFIG_SPI_CLOCK_DIV == 128
494 SPCR |= (BV(SPR1) | BV(SPR0));
495 #elif (CONFIG_SPI_CLOCK_DIV == 64 || CONFIG_SPI_CLOCK_DIV == 32)
497 #elif (CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 8)
499 #elif (CONFIG_SPI_CLOCK_DIV == 4 || CONFIG_SPI_CLOCK_DIV == 2)
500 // SPR0 & SDPR1 both at 0
502 #error Unsupported SPI clock division factor.
505 /* Set SPI2X bit (spi double frequency) */
506 #if (CONFIG_SPI_CLOCK_DIV == 128 || CONFIG_SPI_CLOCK_DIV == 64 \
507 || CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 4)
509 #elif (CONFIG_SPI_CLOCK_DIV == 32 || CONFIG_SPI_CLOCK_DIV == 8 || CONFIG_SPI_CLOCK_DIV == 2)
512 #error Unsupported SPI clock division factor.
515 /* Set clock polarity */
516 #if CONFIG_SPI_CLOCK_POL == 1
520 /* Set clock phase */
521 #if CONFIG_SPI_CLOCK_PHASE == 1
529 static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
535 /* Set all pins as inputs */
536 ATOMIC(SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT) | BV(SPI_SS_BIT)));
539 static void spi_starttx(struct SerialHardware *_hw)
541 struct AvrSerial *hw = (struct AvrSerial *)_hw;
544 IRQ_SAVE_DISABLE(flags);
546 /* Send data only if the SPI is not already transmitting */
547 if (!hw->sending && !fifo_isempty(&ser_handles[SER_SPI]->txfifo))
550 SPDR = fifo_pop(&ser_handles[SER_SPI]->txfifo);
556 static void spi_setbaudrate(
557 UNUSED_ARG(struct SerialHardware *, _hw),
558 UNUSED_ARG(unsigned long, rate))
563 static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
568 static bool tx_sending(struct SerialHardware* _hw)
570 struct AvrSerial *hw = (struct AvrSerial *)_hw;
576 // FIXME: move into compiler.h? Ditch?
578 #define C99INIT(name,val) .name = val
579 #elif defined(__GNUC__)
580 #define C99INIT(name,val) name: val
582 #warning No designated initializers, double check your code
583 #define C99INIT(name,val) (val)
587 * High-level interface data structures
589 static const struct SerialHardwareVT UART0_VT =
591 C99INIT(init, uart0_init),
592 C99INIT(cleanup, uart0_cleanup),
593 C99INIT(setBaudrate, uart0_setbaudrate),
594 C99INIT(setParity, uart0_setparity),
595 C99INIT(txStart, uart0_enabletxirq),
596 C99INIT(txSending, tx_sending),
600 static const struct SerialHardwareVT UART1_VT =
602 C99INIT(init, uart1_init),
603 C99INIT(cleanup, uart1_cleanup),
604 C99INIT(setBaudrate, uart1_setbaudrate),
605 C99INIT(setParity, uart1_setparity),
606 C99INIT(txStart, uart1_enabletxirq),
607 C99INIT(txSending, tx_sending),
609 #endif // AVR_HAS_UART1
611 static const struct SerialHardwareVT SPI_VT =
613 C99INIT(init, spi_init),
614 C99INIT(cleanup, spi_cleanup),
615 C99INIT(setBaudrate, spi_setbaudrate),
616 C99INIT(setParity, spi_setparity),
617 C99INIT(txStart, spi_starttx),
618 C99INIT(txSending, tx_sending),
621 static struct AvrSerial UARTDescs[SER_CNT] =
625 C99INIT(table, &UART0_VT),
626 C99INIT(txbuffer, uart0_txbuffer),
627 C99INIT(rxbuffer, uart0_rxbuffer),
628 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
629 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
631 C99INIT(sending, false),
636 C99INIT(table, &UART1_VT),
637 C99INIT(txbuffer, uart1_txbuffer),
638 C99INIT(rxbuffer, uart1_rxbuffer),
639 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
640 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
642 C99INIT(sending, false),
647 C99INIT(table, &SPI_VT),
648 C99INIT(txbuffer, spi_txbuffer),
649 C99INIT(rxbuffer, spi_rxbuffer),
650 C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
651 C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
653 C99INIT(sending, false),
657 struct SerialHardware *ser_hw_getdesc(int unit)
659 ASSERT(unit < SER_CNT);
660 return &UARTDescs[unit].hw;
668 #if CONFIG_SER_HWHANDSHAKE
670 /// This interrupt is triggered when the CTS line goes high
673 // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
674 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
675 EIMSK &= ~EIMSKF_CTS;
678 #endif // CONFIG_SER_HWHANDSHAKE
682 * Serial 0 TX interrupt handler
684 DECLARE_ISR(USART0_UDRE_vect)
688 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART0]->txfifo;
690 if (fifo_isempty(txfifo))
693 #ifndef SER_UART0_BUS_TXOFF
694 UARTDescs[SER_UART0].sending = false;
697 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
700 // Disable rx interrupt and tx, enable CTS interrupt
702 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
709 char c = fifo_pop(txfifo);
710 SER_UART0_BUS_TXCHAR(c);
716 #ifdef SER_UART0_BUS_TXOFF
718 * Serial port 0 TX complete interrupt handler.
720 * This IRQ is usually disabled. The UDR-empty interrupt
721 * enables it when there's no more data to transmit.
722 * We need to wait until the last character has been
723 * transmitted before switching the 485 transceiver to
726 * The txfifo might have been refilled by putchar() while
727 * we were waiting for the transmission complete interrupt.
728 * In this case, we must restart the UDR empty interrupt,
729 * otherwise we'd stop the serial port with some data
730 * still pending in the buffer.
732 DECLARE_ISR(USART0_TX_vect)
736 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART0]->txfifo;
737 if (fifo_isempty(txfifo))
740 UARTDescs[SER_UART0].sending = false;
743 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
747 #endif /* SER_UART0_BUS_TXOFF */
753 * Serial 1 TX interrupt handler
755 DECLARE_ISR(USART1_UDRE_vect)
759 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART1]->txfifo;
761 if (fifo_isempty(txfifo))
764 #ifndef SER_UART1_BUS_TXOFF
765 UARTDescs[SER_UART1].sending = false;
768 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
771 // Disable rx interrupt and tx, enable CTS interrupt
773 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
780 char c = fifo_pop(txfifo);
781 SER_UART1_BUS_TXCHAR(c);
787 #ifdef SER_UART1_BUS_TXOFF
789 * Serial port 1 TX complete interrupt handler.
791 * \sa port 0 TX complete handler.
793 DECLARE_ISR(USART1_TX_vect)
797 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART1]->txfifo;
798 if (fifo_isempty(txfifo))
801 UARTDescs[SER_UART1].sending = false;
804 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
808 #endif /* SER_UART1_BUS_TXOFF */
810 #endif // AVR_HAS_UART1
814 * Serial 0 RX complete interrupt handler.
816 * This handler is interruptible.
817 * Interrupt are reenabled as soon as recv complete interrupt is
818 * disabled. Using INTERRUPT() is troublesome when the serial
819 * is heavily loaded, because an interrupt could be retriggered
820 * when executing the handler prologue before RXCIE is disabled.
822 * \note The code that re-enables interrupts is commented out
823 * because in some nasty cases the interrupt is retriggered.
824 * This is probably due to the RXC flag being set before
825 * RXCIE is cleared. Unfortunately the RXC flag is read-only
826 * and can't be cleared by code.
828 DECLARE_ISR(USART0_RX_vect)
832 /* Disable Recv complete IRQ */
833 //UCSR0B &= ~BV(RXCIE);
836 /* Should be read before UDR */
837 ser_handles[SER_UART0]->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
839 /* To clear the RXC flag we must _always_ read the UDR even when we're
840 * not going to accept the incoming data, otherwise a new interrupt
841 * will occur once the handler terminates.
844 struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART0]->rxfifo;
846 if (fifo_isfull(rxfifo))
847 ser_handles[SER_UART0]->status |= SERRF_RXFIFOOVERRUN;
850 fifo_push(rxfifo, c);
851 #if CONFIG_SER_HWHANDSHAKE
852 if (fifo_isfull(rxfifo))
857 /* Reenable receive complete int */
859 //UCSR0B |= BV(RXCIE);
868 * Serial 1 RX complete interrupt handler.
870 * This handler is interruptible.
871 * Interrupt are reenabled as soon as recv complete interrupt is
872 * disabled. Using INTERRUPT() is troublesome when the serial
873 * is heavily loaded, because an interrupt could be retriggered
874 * when executing the handler prologue before RXCIE is disabled.
876 * \see DECLARE_ISR(USART1_RX_vect)
878 DECLARE_ISR(USART1_RX_vect)
882 /* Disable Recv complete IRQ */
883 //UCSR1B &= ~BV(RXCIE);
886 /* Should be read before UDR */
887 ser_handles[SER_UART1]->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
889 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
890 * not going to accept the incoming data
893 struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART1]->rxfifo;
894 //ASSERT_VALID_FIFO(rxfifo);
896 if (UNLIKELY(fifo_isfull(rxfifo)))
897 ser_handles[SER_UART1]->status |= SERRF_RXFIFOOVERRUN;
900 fifo_push(rxfifo, c);
901 #if CONFIG_SER_HWHANDSHAKE
902 if (fifo_isfull(rxfifo))
906 /* Re-enable receive complete int */
908 //UCSR1B |= BV(RXCIE);
913 #endif // AVR_HAS_UART1
917 * SPI interrupt handler
919 DECLARE_ISR(SPI_STC_vect)
923 /* Read incoming byte. */
924 if (!fifo_isfull(&ser_handles[SER_SPI]->rxfifo))
925 fifo_push(&ser_handles[SER_SPI]->rxfifo, SPDR);
929 ser_handles[SER_SPI]->status |= SERRF_RXFIFOOVERRUN;
933 if (!fifo_isempty(&ser_handles[SER_SPI]->txfifo))
934 SPDR = fifo_pop(&ser_handles[SER_SPI]->txfifo);
936 UARTDescs[SER_SPI].sending = false;