4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2003, 2004, 2010 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2000 Bernie Innocenti <bernie@codewiz.org>
34 * \brief AVR MEGA UART and SPI I/O driver (Implementation)
36 * \author Bernie Innocenti <bernie@codewiz.org>
37 * \author Stefano Fedrigo <aleph@develer.com>
38 * \author Luca Ottaviano <lottaviano@develer.com>
41 #include "hw/hw_ser.h" /* Required for bus macros overrides */
42 #include <hw/hw_cpufreq.h> /* CPU_FREQ */
44 #include "cfg/cfg_ser.h"
46 #include <cfg/macros.h> /* DIV_ROUND */
47 #include <cfg/debug.h>
48 #include <cfg/cfg_arch.h> // ARCH_NIGHTTEST
51 #include <drv/ser_p.h>
52 #include <drv/timer.h>
54 #include <struct/fifobuf.h>
58 #if defined(__AVR_LIBC_VERSION__) && (__AVR_LIBC_VERSION__ >= 10400UL)
59 #include <avr/interrupt.h>
61 #include <avr/signal.h>
65 #if !CONFIG_SER_HWHANDSHAKE
67 * \name Hardware handshake (RTS/CTS).
70 #define RTS_ON do {} while (0)
71 #define RTS_OFF do {} while (0)
72 #define IS_CTS_ON true
73 #define EIMSKF_CTS 0 /**< Dummy value, must be overridden */
77 #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
78 #define BIT_RXCIE0 RXCIE0
79 #define BIT_RXEN0 RXEN0
80 #define BIT_TXEN0 TXEN0
81 #define BIT_UDRIE0 UDRIE0
83 #define BIT_RXCIE1 RXCIE1
84 #define BIT_RXEN1 RXEN1
85 #define BIT_TXEN1 TXEN1
86 #define BIT_UDRIE1 UDRIE1
87 #if CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
88 #define BIT_RXCIE2 RXCIE2
89 #define BIT_RXEN2 RXEN2
90 #define BIT_TXEN2 TXEN2
91 #define BIT_UDRIE2 UDRIE2
93 #define BIT_RXCIE3 RXCIE3
94 #define BIT_RXEN3 RXEN3
95 #define BIT_TXEN3 TXEN3
96 #define BIT_UDRIE3 UDRIE3
98 #elif CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
99 #define BIT_RXCIE0 RXCIE0
100 #define BIT_RXEN0 RXEN0
101 #define BIT_TXEN0 TXEN0
102 #define BIT_UDRIE0 UDRIE0
104 #define BIT_RXCIE1 RXCIE0
105 #define BIT_RXEN1 RXEN0
106 #define BIT_TXEN1 TXEN0
107 #define BIT_UDRIE1 UDRIE0
109 #define BIT_RXCIE0 RXCIE
110 #define BIT_RXEN0 RXEN
111 #define BIT_TXEN0 TXEN
112 #define BIT_UDRIE0 UDRIE
114 #define BIT_RXCIE1 RXCIE
115 #define BIT_RXEN1 RXEN
116 #define BIT_TXEN1 TXEN
117 #define BIT_UDRIE1 UDRIE
122 * \name Overridable serial bus hooks
124 * These can be redefined in hw.h to implement
125 * special bus policies such as half-duplex, 485, etc.
129 * TXBEGIN TXCHAR TXEND TXOFF
130 * | __________|__________ | |
133 * ______ __ __ __ __ __ __ ________________
134 * \/ \/ \/ \/ \/ \/ \/
135 * ______/\__/\__/\__/\__/\__/\__/
141 #ifndef SER_UART0_BUS_TXINIT
143 * Default TXINIT macro - invoked in uart0_init()
145 * - Enable both the receiver and the transmitter
146 * - Enable only the RX complete interrupt
148 #define SER_UART0_BUS_TXINIT do { \
149 UCSR0A = 0; /* The Arduino Uno bootloader turns on U2X0 */ \
150 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
154 #ifndef SER_UART0_BUS_TXBEGIN
156 * Invoked before starting a transmission
158 * - Enable both the receiver and the transmitter
159 * - Enable both the RX complete and UDR empty interrupts
161 #define SER_UART0_BUS_TXBEGIN do { \
162 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
166 #ifndef SER_UART0_BUS_TXCHAR
168 * Invoked to send one character.
170 #define SER_UART0_BUS_TXCHAR(c) do { \
175 #ifndef SER_UART0_BUS_TXEND
177 * Invoked as soon as the txfifo becomes empty
179 * - Keep both the receiver and the transmitter enabled
180 * - Keep the RX complete interrupt enabled
181 * - Disable the UDR empty interrupt
183 #define SER_UART0_BUS_TXEND do { \
184 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0); \
188 #ifndef SER_UART0_BUS_TXOFF
190 * \def SER_UART0_BUS_TXOFF
192 * Invoked after the last character has been transmitted
194 * The default is no action.
197 #define SER_UART0_BUS_TXOFF
201 #ifndef SER_UART1_BUS_TXINIT
202 /** \sa SER_UART0_BUS_TXINIT */
203 #define SER_UART1_BUS_TXINIT do { \
204 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
207 #ifndef SER_UART1_BUS_TXBEGIN
208 /** \sa SER_UART0_BUS_TXBEGIN */
209 #define SER_UART1_BUS_TXBEGIN do { \
210 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
213 #ifndef SER_UART1_BUS_TXCHAR
214 /** \sa SER_UART0_BUS_TXCHAR */
215 #define SER_UART1_BUS_TXCHAR(c) do { \
219 #ifndef SER_UART1_BUS_TXEND
220 /** \sa SER_UART0_BUS_TXEND */
221 #define SER_UART1_BUS_TXEND do { \
222 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1); \
225 #ifndef SER_UART1_BUS_TXOFF
227 * \def SER_UART1_BUS_TXOFF
229 * \see SER_UART0_BUS_TXOFF
232 #define SER_UART1_BUS_TXOFF
236 #ifndef SER_UART2_BUS_TXINIT
237 /** \sa SER_UART0_BUS_TXINIT */
238 #define SER_UART2_BUS_TXINIT do { \
239 UCSR2B = BV(BIT_RXCIE2) | BV(BIT_RXEN2) | BV(BIT_TXEN2); \
242 #ifndef SER_UART2_BUS_TXBEGIN
243 /** \sa SER_UART0_BUS_TXBEGIN */
244 #define SER_UART2_BUS_TXBEGIN do { \
245 UCSR2B = BV(BIT_RXCIE2) | BV(BIT_UDRIE2) | BV(BIT_RXEN2) | BV(BIT_TXEN2); \
248 #ifndef SER_UART2_BUS_TXCHAR
249 /** \sa SER_UART0_BUS_TXCHAR */
250 #define SER_UART2_BUS_TXCHAR(c) do { \
254 #ifndef SER_UART2_BUS_TXEND
255 /** \sa SER_UART0_BUS_TXEND */
256 #define SER_UART2_BUS_TXEND do { \
257 UCSR2B = BV(BIT_RXCIE2) | BV(BIT_RXEN2) | BV(BIT_TXEN2); \
260 #ifndef SER_UART2_BUS_TXOFF
262 * \def SER_UART2_BUS_TXOFF
264 * \see SER_UART0_BUS_TXOFF
267 #define SER_UART2_BUS_TXOFF
271 #ifndef SER_UART3_BUS_TXINIT
272 /** \sa SER_UART0_BUS_TXINIT */
273 #define SER_UART3_BUS_TXINIT do { \
274 UCSR3B = BV(BIT_RXCIE3) | BV(BIT_RXEN3) | BV(BIT_TXEN3); \
277 #ifndef SER_UART3_BUS_TXBEGIN
278 /** \sa SER_UART0_BUS_TXBEGIN */
279 #define SER_UART3_BUS_TXBEGIN do { \
280 UCSR3B = BV(BIT_RXCIE3) | BV(BIT_UDRIE3) | BV(BIT_RXEN3) | BV(BIT_TXEN3); \
283 #ifndef SER_UART3_BUS_TXCHAR
284 /** \sa SER_UART0_BUS_TXCHAR */
285 #define SER_UART3_BUS_TXCHAR(c) do { \
289 #ifndef SER_UART3_BUS_TXEND
290 /** \sa SER_UART0_BUS_TXEND */
291 #define SER_UART3_BUS_TXEND do { \
292 UCSR3B = BV(BIT_RXCIE3) | BV(BIT_RXEN3) | BV(BIT_TXEN3); \
295 #ifndef SER_UART3_BUS_TXOFF
297 * \def SER_UART3_BUS_TXOFF
299 * \see SER_UART0_BUS_TXOFF
302 #define SER_UART3_BUS_TXOFF
309 * \name Overridable SPI hooks
311 * These can be redefined in hw.h to implement
312 * special bus policies such as slave select pin handling, etc.
316 #ifndef SER_SPI_BUS_TXINIT
318 * Default TXINIT macro - invoked in spi_init()
319 * The default is no action.
321 #define SER_SPI_BUS_TXINIT
324 #ifndef SER_SPI_BUS_TXCLOSE
326 * Invoked after the last character has been transmitted.
327 * The default is no action.
329 #define SER_SPI_BUS_TXCLOSE
334 /* SPI port and pin configuration */
335 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103 || CPU_AVR_ATMEGA1281 \
336 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
337 #define SPI_PORT PORTB
339 #define SPI_SS_BIT PB0
340 #define SPI_SCK_BIT PB1
341 #define SPI_MOSI_BIT PB2
342 #define SPI_MISO_BIT PB3
343 // TODO: these bits are the same as ATMEGA8 but the defines in avr-gcc are different.
344 // They should be the same!
345 #elif CPU_AVR_ATMEGA328P
346 #define SPI_PORT PORTB
348 #define SPI_SS_BIT PORTB2
349 #define SPI_SCK_BIT PORTB5
350 #define SPI_MOSI_BIT PORTB3
351 #define SPI_MISO_BIT PORTB4
352 #elif CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA168
353 #define SPI_PORT PORTB
355 #define SPI_SS_BIT PB2
356 #define SPI_SCK_BIT PB5
357 #define SPI_MOSI_BIT PB3
358 #define SPI_MISO_BIT PB4
359 #elif CPU_AVR_ATMEGA32
360 #define SPI_PORT PORTB
362 #define SPI_SS_BIT PB4
363 #define SPI_SCK_BIT PB7
364 #define SPI_MOSI_BIT PB5
365 #define SPI_MISO_BIT PB6
367 #error Unknown architecture
370 /* USART register definitions */
371 #if CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
372 #define AVR_HAS_UART1 1
373 #define AVR_HAS_UART2 1
374 #define AVR_HAS_UART3 1
375 #elif CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA1281
376 #define AVR_HAS_UART1 1
377 #define AVR_HAS_UART2 0
378 #define AVR_HAS_UART3 0
379 #elif CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
380 #define AVR_HAS_UART1 0
381 #define AVR_HAS_UART2 0
382 #define AVR_HAS_UART3 0
383 #define USART0_UDRE_vect USART_UDRE_vect
384 #define USART0_RX_vect USART_RX_vect
385 #define USART0_TX_vect USART_TX_vect
386 #elif CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA32
387 #define AVR_HAS_UART1 0
388 #define AVR_HAS_UART2 0
389 #define AVR_HAS_UART3 0
398 #define USART0_UDRE_vect USART_UDRE_vect
399 #define USART0_RX_vect USART_RXC_vect
400 #define USART0_TX_vect USART_TXC_vect
401 #elif CPU_AVR_ATMEGA103
402 #define AVR_HAS_UART1 0
403 #define AVR_HAS_UART2 0
404 #define AVR_HAS_UART3 0
409 #define USART0_UDRE_vect USART_UDRE_vect
410 #define USART0_RX_vect USART_RX_vect
411 #define USART0_TX_vect USART_TX_vect
413 #error Unknown architecture
417 /* From the high-level serial driver */
418 extern struct Serial *ser_handles[SER_CNT];
420 /* TX and RX buffers */
421 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
422 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
424 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
425 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
428 static unsigned char uart2_txbuffer[CONFIG_UART2_TXBUFSIZE];
429 static unsigned char uart2_rxbuffer[CONFIG_UART2_RXBUFSIZE];
432 static unsigned char uart3_txbuffer[CONFIG_UART3_TXBUFSIZE];
433 static unsigned char uart3_rxbuffer[CONFIG_UART3_RXBUFSIZE];
435 static unsigned char spi_txbuffer[CONFIG_SPI_TXBUFSIZE];
436 static unsigned char spi_rxbuffer[CONFIG_SPI_RXBUFSIZE];
440 * Internal hardware state structure
442 * The \a sending variable is true while the transmission
443 * interrupt is retriggering itself.
445 * For the USARTs the \a sending flag is useful for taking specific
446 * actions before sending a burst of data, at the start of a trasmission
447 * but not before every char sent.
449 * For the SPI, this flag is necessary because the SPI sends and receives
450 * bytes at the same time and the SPI IRQ is unique for send/receive.
451 * The only way to start transmission is to write data in SPDR (this
452 * is done by spi_starttx()). We do this *only* if a transfer is
453 * not already started.
457 struct SerialHardware hw;
458 volatile bool sending;
461 static uint16_t uart_period(unsigned long bps)
463 uint16_t period = DIV_ROUND(CPU_FREQ / 16UL, bps) - 1;
466 long skew = bps - (long)(period + 1) * (CPU_FREQ / 16);
467 /* 8N1 is reliable within 3% skew */
468 if ((unsigned long)ABS(skew) > bps / (100 / 3))
469 kprintf("Baudrate off by %ldbps\n", skew);
472 //DB(kprintf("uart_period(bps=%lu): period=%u\n", bps, period);)
479 static void uart0_init(
480 UNUSED_ARG(struct SerialHardware *, _hw),
481 UNUSED_ARG(struct Serial *, ser))
483 SER_UART0_BUS_TXINIT;
488 static void uart0_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
493 static void uart0_enabletxirq(struct SerialHardware *_hw)
495 struct AvrSerial *hw = (struct AvrSerial *)_hw;
498 * WARNING: racy code here! The tx interrupt sets hw->sending to false
499 * when it runs with an empty fifo. The order of statements in the
505 SER_UART0_BUS_TXBEGIN;
509 static void uart0_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
511 uint16_t period = uart_period(rate);
513 #if !CPU_AVR_ATMEGA103
514 UBRR0H = period >> 8;
519 static void uart0_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
521 #if !CPU_AVR_ATMEGA103
522 UCSR0C = (UCSR0C & ~(BV(UPM01) | BV(UPM00))) | ((parity) << UPM00);
528 static void uart1_init(
529 UNUSED_ARG(struct SerialHardware *, _hw),
530 UNUSED_ARG(struct Serial *, ser))
532 SER_UART1_BUS_TXINIT;
537 static void uart1_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
542 static void uart1_enabletxirq(struct SerialHardware *_hw)
544 struct AvrSerial *hw = (struct AvrSerial *)_hw;
547 * WARNING: racy code here! The tx interrupt
548 * sets hw->sending to false when it runs with
549 * an empty fifo. The order of the statements
550 * in the if-block matters.
555 SER_UART1_BUS_TXBEGIN;
559 static void uart1_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
561 uint16_t period = uart_period(rate);
562 UBRR1H = period >> 8;
566 static void uart1_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
568 UCSR1C = (UCSR1C & ~(BV(UPM11) | BV(UPM10))) | ((parity) << UPM10);
571 #endif // AVR_HAS_UART1
575 static void uart2_init(
576 UNUSED_ARG(struct SerialHardware *, _hw),
577 UNUSED_ARG(struct Serial *, ser))
579 SER_UART2_BUS_TXINIT;
584 static void uart2_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
589 static void uart2_enabletxirq(struct SerialHardware *_hw)
591 struct AvrSerial *hw = (struct AvrSerial *)_hw;
594 * WARNING: racy code here! The tx interrupt
595 * sets hw->sending to false when it runs with
596 * an empty fifo. The order of the statements
597 * in the if-block matters.
602 SER_UART2_BUS_TXBEGIN;
606 static void uart2_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
608 uint16_t period = uart_period(rate);
609 UBRR2H = period >> 8;
613 static void uart2_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
615 UCSR2C = (UCSR2C & ~(BV(UPM21) | BV(UPM20))) | ((parity) << UPM20);
618 #endif // AVR_HAS_UART2
622 static void uart3_init(
623 UNUSED_ARG(struct SerialHardware *, _hw),
624 UNUSED_ARG(struct Serial *, ser))
626 SER_UART3_BUS_TXINIT;
631 static void uart3_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
636 static void uart3_enabletxirq(struct SerialHardware *_hw)
638 struct AvrSerial *hw = (struct AvrSerial *)_hw;
641 * WARNING: racy code here! The tx interrupt
642 * sets hw->sending to false when it runs with
643 * an empty fifo. The order of the statements
644 * in the if-block matters.
649 SER_UART3_BUS_TXBEGIN;
653 static void uart3_setbaudrate(UNUSED_ARG(struct SerialHardware *, _hw), unsigned long rate)
655 uint16_t period = uart_period(rate);
656 UBRR3H = period >> 8;
660 static void uart3_setparity(UNUSED_ARG(struct SerialHardware *, _hw), int parity)
662 UCSR3C = (UCSR3C & ~(BV(UPM31) | BV(UPM30))) | ((parity) << UPM30);
665 #endif // AVR_HAS_UART3
668 static void spi_init(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(struct Serial *, ser))
671 * Set MOSI and SCK ports out, MISO in.
673 * The ATmega64/128 datasheet explicitly states that the input/output
674 * state of the SPI pins is not significant, as when the SPI is
675 * active the I/O port are overrided.
676 * This is *blatantly FALSE*.
678 * Moreover, the MISO pin on the board_kc *must* be in high impedance
679 * state even when the SPI is off, because the line is wired together
680 * with the KBus serial RX, and the transmitter of the slave boards
681 * would be unable to drive the line.
683 ATOMIC(SPI_DDR |= (BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT)));
686 * If the SPI master mode is activated and the SS pin is in input and tied low,
687 * the SPI hardware will automatically switch to slave mode!
688 * For proper communication this pins should therefore be:
690 * - as input but tied high forever!
691 * This driver set the pin as output.
693 #warning FIXME:SPI SS pin set as output for proper operation, check schematics for possible conflicts.
694 ATOMIC(SPI_DDR |= BV(SPI_SS_BIT));
696 ATOMIC(SPI_DDR &= ~BV(SPI_MISO_BIT));
697 /* Enable SPI, IRQ on, Master */
698 SPCR = BV(SPE) | BV(SPIE) | BV(MSTR);
701 #if CONFIG_SPI_DATA_ORDER == SER_LSB_FIRST
705 /* Set SPI clock rate */
706 #if CONFIG_SPI_CLOCK_DIV == 128
707 SPCR |= (BV(SPR1) | BV(SPR0));
708 #elif (CONFIG_SPI_CLOCK_DIV == 64 || CONFIG_SPI_CLOCK_DIV == 32)
710 #elif (CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 8)
712 #elif (CONFIG_SPI_CLOCK_DIV == 4 || CONFIG_SPI_CLOCK_DIV == 2)
713 // SPR0 & SDPR1 both at 0
715 #error Unsupported SPI clock division factor.
718 /* Set SPI2X bit (spi double frequency) */
719 #if (CONFIG_SPI_CLOCK_DIV == 128 || CONFIG_SPI_CLOCK_DIV == 64 \
720 || CONFIG_SPI_CLOCK_DIV == 16 || CONFIG_SPI_CLOCK_DIV == 4)
722 #elif (CONFIG_SPI_CLOCK_DIV == 32 || CONFIG_SPI_CLOCK_DIV == 8 || CONFIG_SPI_CLOCK_DIV == 2)
725 #error Unsupported SPI clock division factor.
728 /* Set clock polarity */
729 #if CONFIG_SPI_CLOCK_POL == 1
733 /* Set clock phase */
734 #if CONFIG_SPI_CLOCK_PHASE == 1
742 static void spi_cleanup(UNUSED_ARG(struct SerialHardware *, _hw))
748 /* Set all pins as inputs */
749 ATOMIC(SPI_DDR &= ~(BV(SPI_MISO_BIT) | BV(SPI_MOSI_BIT) | BV(SPI_SCK_BIT) | BV(SPI_SS_BIT)));
752 static void spi_starttx(struct SerialHardware *_hw)
754 struct AvrSerial *hw = (struct AvrSerial *)_hw;
757 IRQ_SAVE_DISABLE(flags);
759 /* Send data only if the SPI is not already transmitting */
760 if (!hw->sending && !fifo_isempty(&ser_handles[SER_SPI]->txfifo))
763 SPDR = fifo_pop(&ser_handles[SER_SPI]->txfifo);
769 static void spi_setbaudrate(
770 UNUSED_ARG(struct SerialHardware *, _hw),
771 UNUSED_ARG(unsigned long, rate))
776 static void spi_setparity(UNUSED_ARG(struct SerialHardware *, _hw), UNUSED_ARG(int, parity))
781 static bool tx_sending(struct SerialHardware* _hw)
783 struct AvrSerial *hw = (struct AvrSerial *)_hw;
789 // FIXME: move into compiler.h? Ditch?
791 #define C99INIT(name,val) .name = val
792 #elif defined(__GNUC__)
793 #define C99INIT(name,val) name: val
795 #warning No designated initializers, double check your code
796 #define C99INIT(name,val) (val)
800 * High-level interface data structures
802 static const struct SerialHardwareVT UART0_VT =
804 C99INIT(init, uart0_init),
805 C99INIT(cleanup, uart0_cleanup),
806 C99INIT(setBaudrate, uart0_setbaudrate),
807 C99INIT(setParity, uart0_setparity),
808 C99INIT(txStart, uart0_enabletxirq),
809 C99INIT(txSending, tx_sending),
813 static const struct SerialHardwareVT UART1_VT =
815 C99INIT(init, uart1_init),
816 C99INIT(cleanup, uart1_cleanup),
817 C99INIT(setBaudrate, uart1_setbaudrate),
818 C99INIT(setParity, uart1_setparity),
819 C99INIT(txStart, uart1_enabletxirq),
820 C99INIT(txSending, tx_sending),
822 #endif // AVR_HAS_UART1
825 static const struct SerialHardwareVT UART2_VT =
827 C99INIT(init, uart2_init),
828 C99INIT(cleanup, uart2_cleanup),
829 C99INIT(setBaudrate, uart2_setbaudrate),
830 C99INIT(setParity, uart2_setparity),
831 C99INIT(txStart, uart2_enabletxirq),
832 C99INIT(txSending, tx_sending),
834 #endif // AVR_HAS_UART2
837 static const struct SerialHardwareVT UART3_VT =
839 C99INIT(init, uart3_init),
840 C99INIT(cleanup, uart3_cleanup),
841 C99INIT(setBaudrate, uart3_setbaudrate),
842 C99INIT(setParity, uart3_setparity),
843 C99INIT(txStart, uart3_enabletxirq),
844 C99INIT(txSending, tx_sending),
846 #endif // AVR_HAS_UART3
848 static const struct SerialHardwareVT SPI_VT =
850 C99INIT(init, spi_init),
851 C99INIT(cleanup, spi_cleanup),
852 C99INIT(setBaudrate, spi_setbaudrate),
853 C99INIT(setParity, spi_setparity),
854 C99INIT(txStart, spi_starttx),
855 C99INIT(txSending, tx_sending),
858 static struct AvrSerial UARTDescs[SER_CNT] =
862 C99INIT(table, &UART0_VT),
863 C99INIT(txbuffer, uart0_txbuffer),
864 C99INIT(rxbuffer, uart0_rxbuffer),
865 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
866 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
868 C99INIT(sending, false),
873 C99INIT(table, &UART1_VT),
874 C99INIT(txbuffer, uart1_txbuffer),
875 C99INIT(rxbuffer, uart1_rxbuffer),
876 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
877 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
879 C99INIT(sending, false),
885 C99INIT(table, &UART2_VT),
886 C99INIT(txbuffer, uart2_txbuffer),
887 C99INIT(rxbuffer, uart2_rxbuffer),
888 C99INIT(txbuffer_size, sizeof(uart2_txbuffer)),
889 C99INIT(rxbuffer_size, sizeof(uart2_rxbuffer)),
891 C99INIT(sending, false),
897 C99INIT(table, &UART3_VT),
898 C99INIT(txbuffer, uart3_txbuffer),
899 C99INIT(rxbuffer, uart3_rxbuffer),
900 C99INIT(txbuffer_size, sizeof(uart3_txbuffer)),
901 C99INIT(rxbuffer_size, sizeof(uart3_rxbuffer)),
903 C99INIT(sending, false),
908 C99INIT(table, &SPI_VT),
909 C99INIT(txbuffer, spi_txbuffer),
910 C99INIT(rxbuffer, spi_rxbuffer),
911 C99INIT(txbuffer_size, sizeof(spi_txbuffer)),
912 C99INIT(rxbuffer_size, sizeof(spi_rxbuffer)),
914 C99INIT(sending, false),
918 struct SerialHardware *ser_hw_getdesc(int unit)
920 ASSERT(unit < SER_CNT);
921 return &UARTDescs[unit].hw;
929 #if CONFIG_SER_HWHANDSHAKE
931 /// This interrupt is triggered when the CTS line goes high
934 // Re-enable UDR empty interrupt and TX, then disable CTS interrupt
935 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
936 EIMSK &= ~EIMSKF_CTS;
939 #endif // CONFIG_SER_HWHANDSHAKE
943 * Serial 0 TX interrupt handler
945 DECLARE_ISR(USART0_UDRE_vect)
949 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART0]->txfifo;
951 if (fifo_isempty(txfifo))
954 #ifndef SER_UART0_BUS_TXOFF
955 UARTDescs[SER_UART0].sending = false;
958 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
961 // Disable rx interrupt and tx, enable CTS interrupt
963 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
970 char c = fifo_pop(txfifo);
971 SER_UART0_BUS_TXCHAR(c);
977 #ifdef SER_UART0_BUS_TXOFF
979 * Serial port 0 TX complete interrupt handler.
981 * This IRQ is usually disabled. The UDR-empty interrupt
982 * enables it when there's no more data to transmit.
983 * We need to wait until the last character has been
984 * transmitted before switching the 485 transceiver to
987 * The txfifo might have been refilled by putchar() while
988 * we were waiting for the transmission complete interrupt.
989 * In this case, we must restart the UDR empty interrupt,
990 * otherwise we'd stop the serial port with some data
991 * still pending in the buffer.
993 DECLARE_ISR(USART0_TX_vect)
997 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART0]->txfifo;
998 if (fifo_isempty(txfifo))
1000 SER_UART0_BUS_TXOFF;
1001 UARTDescs[SER_UART0].sending = false;
1004 UCSR0B = BV(BIT_RXCIE0) | BV(BIT_UDRIE0) | BV(BIT_RXEN0) | BV(BIT_TXEN0);
1008 #endif /* SER_UART0_BUS_TXOFF */
1014 * Serial 1 TX interrupt handler
1016 DECLARE_ISR(USART1_UDRE_vect)
1020 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART1]->txfifo;
1022 if (fifo_isempty(txfifo))
1024 SER_UART1_BUS_TXEND;
1025 #ifndef SER_UART1_BUS_TXOFF
1026 UARTDescs[SER_UART1].sending = false;
1029 #if CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA103
1030 else if (!IS_CTS_ON)
1032 // Disable rx interrupt and tx, enable CTS interrupt
1034 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
1036 EIMSK |= EIMSKF_CTS;
1041 char c = fifo_pop(txfifo);
1042 SER_UART1_BUS_TXCHAR(c);
1048 #ifdef SER_UART1_BUS_TXOFF
1050 * Serial port 1 TX complete interrupt handler.
1052 * \sa port 0 TX complete handler.
1054 DECLARE_ISR(USART1_TX_vect)
1058 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART1]->txfifo;
1059 if (fifo_isempty(txfifo))
1061 SER_UART1_BUS_TXOFF;
1062 UARTDescs[SER_UART1].sending = false;
1065 UCSR1B = BV(BIT_RXCIE1) | BV(BIT_UDRIE1) | BV(BIT_RXEN1) | BV(BIT_TXEN1);
1069 #endif /* SER_UART1_BUS_TXOFF */
1071 #endif // AVR_HAS_UART1
1076 * Serial 2 TX interrupt handler
1078 DECLARE_ISR(USART2_UDRE_vect)
1082 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART2]->txfifo;
1084 if (fifo_isempty(txfifo))
1086 SER_UART2_BUS_TXEND;
1087 #ifndef SER_UART2_BUS_TXOFF
1088 UARTDescs[SER_UART2].sending = false;
1093 char c = fifo_pop(txfifo);
1094 SER_UART2_BUS_TXCHAR(c);
1100 #ifdef SER_UART2_BUS_TXOFF
1102 * Serial port 2 TX complete interrupt handler.
1104 * \sa port 0 TX complete handler.
1106 DECLARE_ISR(USART2_TX_vect)
1110 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART2]->txfifo;
1111 if (fifo_isempty(txfifo))
1113 SER_UART2_BUS_TXOFF;
1114 UARTDescs[SER_UART2].sending = false;
1117 UCSR2B = BV(BIT_RXCIE2) | BV(BIT_UDRIE2) | BV(BIT_RXEN2) | BV(BIT_TXEN2);
1121 #endif /* SER_UART2_BUS_TXOFF */
1123 #endif // AVR_HAS_UART2
1128 * Serial 3 TX interrupt handler
1130 DECLARE_ISR(USART3_UDRE_vect)
1134 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART3]->txfifo;
1136 if (fifo_isempty(txfifo))
1138 SER_UART3_BUS_TXEND;
1139 #ifndef SER_UART3_BUS_TXOFF
1140 UARTDescs[SER_UART3].sending = false;
1145 char c = fifo_pop(txfifo);
1146 SER_UART3_BUS_TXCHAR(c);
1152 #ifdef SER_UART3_BUS_TXOFF
1154 * Serial port 3 TX complete interrupt handler.
1156 * \sa port 0 TX complete handler.
1158 DECLARE_ISR(USART3_TX_vect)
1162 struct FIFOBuffer * const txfifo = &ser_handles[SER_UART3]->txfifo;
1163 if (fifo_isempty(txfifo))
1165 SER_UART3_BUS_TXOFF;
1166 UARTDescs[SER_UART3].sending = false;
1169 UCSR3B = BV(BIT_RXCIE3) | BV(BIT_UDRIE3) | BV(BIT_RXEN3) | BV(BIT_TXEN3);
1173 #endif /* SER_UART3_BUS_TXOFF */
1175 #endif // AVR_HAS_UART3
1179 * Serial 0 RX complete interrupt handler.
1181 * This handler is interruptible.
1182 * Interrupt are reenabled as soon as recv complete interrupt is
1183 * disabled. Using INTERRUPT() is troublesome when the serial
1184 * is heavily loaded, because an interrupt could be retriggered
1185 * when executing the handler prologue before RXCIE is disabled.
1187 * \note The code that re-enables interrupts is commented out
1188 * because in some nasty cases the interrupt is retriggered.
1189 * This is probably due to the RXC flag being set before
1190 * RXCIE is cleared. Unfortunately the RXC flag is read-only
1191 * and can't be cleared by code.
1193 DECLARE_ISR(USART0_RX_vect)
1197 /* Disable Recv complete IRQ */
1198 //UCSR0B &= ~BV(RXCIE);
1201 /* Should be read before UDR */
1202 ser_handles[SER_UART0]->status |= UCSR0A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
1204 /* To clear the RXC flag we must _always_ read the UDR even when we're
1205 * not going to accept the incoming data, otherwise a new interrupt
1206 * will occur once the handler terminates.
1209 struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART0]->rxfifo;
1211 if (fifo_isfull(rxfifo))
1212 ser_handles[SER_UART0]->status |= SERRF_RXFIFOOVERRUN;
1215 fifo_push(rxfifo, c);
1216 #if CONFIG_SER_HWHANDSHAKE
1217 if (fifo_isfull(rxfifo))
1222 /* Reenable receive complete int */
1224 //UCSR0B |= BV(RXCIE);
1233 * Serial 1 RX complete interrupt handler.
1235 * This handler is interruptible.
1236 * Interrupt are reenabled as soon as recv complete interrupt is
1237 * disabled. Using INTERRUPT() is troublesome when the serial
1238 * is heavily loaded, because an interrupt could be retriggered
1239 * when executing the handler prologue before RXCIE is disabled.
1241 * \see DECLARE_ISR(USART1_RX_vect)
1243 DECLARE_ISR(USART1_RX_vect)
1247 /* Disable Recv complete IRQ */
1248 //UCSR1B &= ~BV(RXCIE);
1251 /* Should be read before UDR */
1252 ser_handles[SER_UART1]->status |= UCSR1A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
1254 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
1255 * not going to accept the incoming data
1258 struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART1]->rxfifo;
1259 //ASSERT_VALID_FIFO(rxfifo);
1261 if (UNLIKELY(fifo_isfull(rxfifo)))
1262 ser_handles[SER_UART1]->status |= SERRF_RXFIFOOVERRUN;
1265 fifo_push(rxfifo, c);
1266 #if CONFIG_SER_HWHANDSHAKE
1267 if (fifo_isfull(rxfifo))
1271 /* Re-enable receive complete int */
1273 //UCSR1B |= BV(RXCIE);
1278 #endif // AVR_HAS_UART1
1283 * Serial 2 RX complete interrupt handler.
1285 * This handler is interruptible.
1286 * Interrupt are reenabled as soon as recv complete interrupt is
1287 * disabled. Using INTERRUPT() is troublesome when the serial
1288 * is heavily loaded, because an interrupt could be retriggered
1289 * when executing the handler prologue before RXCIE is disabled.
1291 * \see DECLARE_ISR(USART2_RX_vect)
1293 DECLARE_ISR(USART2_RX_vect)
1297 /* Disable Recv complete IRQ */
1298 //UCSR1B &= ~BV(RXCIE);
1301 /* Should be read before UDR */
1302 ser_handles[SER_UART2]->status |= UCSR2A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
1304 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
1305 * not going to accept the incoming data
1308 struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART2]->rxfifo;
1309 //ASSERT_VALID_FIFO(rxfifo);
1311 if (UNLIKELY(fifo_isfull(rxfifo)))
1312 ser_handles[SER_UART2]->status |= SERRF_RXFIFOOVERRUN;
1315 fifo_push(rxfifo, c);
1316 #if CONFIG_SER_HWHANDSHAKE
1317 if (fifo_isfull(rxfifo))
1321 /* Re-enable receive complete int */
1323 //UCSR1B |= BV(RXCIE);
1328 #endif // AVR_HAS_UART2
1333 * Serial 3 RX complete interrupt handler.
1335 * This handler is interruptible.
1336 * Interrupt are reenabled as soon as recv complete interrupt is
1337 * disabled. Using INTERRUPT() is troublesome when the serial
1338 * is heavily loaded, because an interrupt could be retriggered
1339 * when executing the handler prologue before RXCIE is disabled.
1341 * \see DECLARE_ISR(USART3_RX_vect)
1343 DECLARE_ISR(USART3_RX_vect)
1347 /* Disable Recv complete IRQ */
1348 //UCSR1B &= ~BV(RXCIE);
1351 /* Should be read before UDR */
1352 ser_handles[SER_UART3]->status |= UCSR3A & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
1354 /* To avoid an IRQ storm, we must _always_ read the UDR even when we're
1355 * not going to accept the incoming data
1358 struct FIFOBuffer * const rxfifo = &ser_handles[SER_UART3]->rxfifo;
1359 //ASSERT_VALID_FIFO(rxfifo);
1361 if (UNLIKELY(fifo_isfull(rxfifo)))
1362 ser_handles[SER_UART3]->status |= SERRF_RXFIFOOVERRUN;
1365 fifo_push(rxfifo, c);
1366 #if CONFIG_SER_HWHANDSHAKE
1367 if (fifo_isfull(rxfifo))
1371 /* Re-enable receive complete int */
1373 //UCSR1B |= BV(RXCIE);
1378 #endif // AVR_HAS_UART3
1382 * SPI interrupt handler
1384 DECLARE_ISR(SPI_STC_vect)
1388 /* Read incoming byte. */
1389 if (!fifo_isfull(&ser_handles[SER_SPI]->rxfifo))
1390 fifo_push(&ser_handles[SER_SPI]->rxfifo, SPDR);
1394 ser_handles[SER_SPI]->status |= SERRF_RXFIFOOVERRUN;
1398 if (!fifo_isempty(&ser_handles[SER_SPI]->txfifo))
1399 SPDR = fifo_pop(&ser_handles[SER_SPI]->txfifo);
1401 UARTDescs[SER_SPI].sending = false;