4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2003, 2004, 2010 Develer S.r.l. (http://www.develer.com/)
30 * Copyright 2011 Onno <developer@gorgoz.org>
34 * \brief AVR XMEGA USART driver (Implementation)
36 * This file is heavily inspired by the AVR implementation for BeRTOS,
37 * but uses a different approach for implementing the different debug
38 * ports, by using the USART_t structs.
40 * \author Onno <developer@gorgoz.org>
43 #include "hw/hw_ser.h" /* Required for bus macros overrides */
44 #include <hw/hw_cpufreq.h> /* CPU_FREQ */
46 #include "cfg/cfg_ser.h" /* Serialport configuration settings */
48 #include <cfg/macros.h> /* DIV_ROUND */
49 #include <cfg/debug.h> /* debug configuration */
52 #include <drv/ser_p.h>
53 #include <drv/timer.h>
55 #include <struct/fifobuf.h>
57 #include <avr/io.h> /* AVR IO ports and structures */
58 #include <avr/interrupt.h> /* AVR Interrupt methods */
61 * Scalefactor to use for computing the baudrate
62 * this scalefactor should be an integer value between -7
65 #ifndef USART_SCALE_FACTOR
66 #define USART_SCALE_FACTOR (-7)
68 #if USART_SCALE_FACTOR > 7 || USART_SCALE_FACTOR < -7
69 #error USART_SCALE_FACTOR should be an integer between -7 and 7
73 /* Helper macros, mostly taken from the Atmel Examples
74 * Slightly alterd to match the BeRTOS naming convention
77 /* \brief Set USART baud rate.
79 * Sets the USART's baud rate register.
81 * UBRR_Value : Value written to UBRR
82 * ScaleFactor : Time Base Generator Scale Factor
84 * Equation for calculation of BSEL value in asynchronous normal speed mode:
86 * BSEL = ((I/O clock frequency)/(2^(ScaleFactor)*16*Baudrate))-1
88 * BSEL = (1/(2^(ScaleFactor)*16))*(((I/O clock frequency)/Baudrate)-1)
90 * \note See XMEGA manual for equations for calculation of BSEL value in other
93 * \param _usart Pointer to the USART module.
94 * \param _bselValue Value to write to BSEL part of Baud control register.
96 * \param _bScaleFactor USART baud rate scale factor.
99 #define USART_SET_BAUDRATE(_usart, _bselValue, _bScaleFactor) \
100 (_usart)->BAUDCTRLA =(uint8_t)_bselValue; \
101 (_usart)->BAUDCTRLB =(_bScaleFactor << USART_BSCALE0_bp)|(_bselValue >> 8)
103 /* \brief Enable USART receiver.
105 * \param _usart Pointer to the USART module
107 #define USART_RX_ENABLE(_usart) ((_usart)->CTRLB |= USART_RXEN_bm)
109 /* \brief Disable USART receiver.
111 * \param _usart Pointer to the USART module.
113 #define USART_RX_DISABLE(_usart) ((_usart)->CTRLB &= ~USART_RXEN_bm)
115 /* \brief Enable USART transmitter.
117 * \param _usart Pointer to the USART module.
119 #define USART_TX_ENABLE(_usart) ((_usart)->CTRLB |= USART_TXEN_bm)
121 /* \brief Disable USART transmitter.
123 * \param _usart Pointer to the USART module.
125 #define USART_TX_DISABLE(_usart) ((_usart)->CTRLB &= ~USART_TXEN_bm)
127 /* \brief Set USART RXD interrupt level.
129 * Sets the interrupt level on RX Complete interrupt.
131 * \param _usart Pointer to the USART module.
132 * \param _rxdIntLevel Interrupt level of the RXD interrupt.
133 * Use USART_RXCINTLVL_t type.
135 #define USART_SET_RX_INTERRUPT_LEVEL(_usart, _rxdIntLevel) \
136 ((_usart)->CTRLA = ((_usart)->CTRLA & ~USART_RXCINTLVL_gm) | _rxdIntLevel)
138 /* \brief Set USART TXD interrupt level.
140 * Sets the interrupt level on TX Complete interrupt.
142 * \param _usart Pointer to the USART module.
143 * \param _txdIntLevel Interrupt level of the TXD interrupt.
144 * Use USART_TXCINTLVL_t type.
146 #define USART_SET_TX_INTERRUPT_LEVEL(_usart, _txdIntLevel) \
147 (_usart)->CTRLA = ((_usart)->CTRLA & ~USART_TXCINTLVL_gm) | _txdIntLevel
149 /* \brief Set USART DRE interrupt level.
151 * Sets the interrupt level on Data Register interrupt.
153 * \param _usart Pointer to the USART module.
154 * \param _dreIntLevel Interrupt level of the DRE interrupt.
155 * Use USART_DREINTLVL_t type.
157 #define USART_SET_DRE_INTERRUPT_LEVEL(_usart, _dreIntLevel) \
158 (_usart)->CTRLA = ((_usart)->CTRLA & ~USART_DREINTLVL_gm) | _dreIntLevel
160 /* \brief Set the mode the USART run in.
162 * Set the mode the USART run in. The default mode is asynchronous mode.
164 * \param _usart Pointer to the USART module register section.
165 * \param _usartMode Selects the USART mode. Use USART_CMODE_t type.
168 * - 0x0 : Asynchronous mode.
169 * - 0x1 : Synchronous mode.
171 * - 0x3 : Master SPI mode.
173 #define USART_SET_MODE(_usart, _usartMode) \
174 ((_usart)->CTRLC = ((_usart)->CTRLC & (~USART_CMODE_gm)) | _usartMode)
176 /* \brief Check if data register empty flag is set.
178 * \param _usart The USART module.
180 #define USART_IS_TX_DATA_REGISTER_EMPTY(_usart) (((_usart)->STATUS & USART_DREIF_bm) != 0)
182 /* \brief Put data (5-8 bit character).
184 * Use the macro USART_IsTXDataRegisterEmpty before using this function to
185 * put data to the TX register.
187 * \param _usart The USART module.
188 * \param _data The data to send.
190 #define USART_PUT_CHAR(_usart, _data) ((_usart)->DATA = _data)
192 /* \brief Checks if the RX complete interrupt flag is set.
194 * Checks if the RX complete interrupt flag is set.
196 * \param _usart The USART module.
198 #define USART_IS_RX_COMPLETE(_usart) (((_usart)->STATUS & USART_RXCIF_bm) != 0)
200 /* \brief Get received data (5-8 bit character).
202 * This macro reads out the RX register.
203 * Use the macro USART_RX_Complete to check if anything is received.
205 * \param _usart The USART module.
207 * \retval Received data.
209 #define USART_GET_CHAR(_usart) ((_usart)->DATA)
211 /* configurable macros */
213 #if !CONFIG_SER_HWHANDSHAKE
215 * \name Hardware handshake (RTS/CTS).
218 #define RTS_ON do {} while (0)
219 #define RTS_OFF do {} while (0)
220 #define IS_CTS_ON true
221 #define EIMSKF_CTS 0 /**< Dummy value, must be overridden */
226 * \name Overridable serial bus hooks
228 * These can be redefined in hw.h to implement
229 * special bus policies such as half-duplex, 485, etc.
233 * TXBEGIN TXCHAR TXEND TXOFF
234 * | __________|__________ | |
237 * ______ __ __ __ __ __ __ ________________
238 * \/ \/ \/ \/ \/ \/ \/
239 * ______/\__/\__/\__/\__/\__/\__/
246 #ifndef SER_UART_BUS_TXINIT
248 * Default TXINIT macro - invoked in uart_init()
250 * - Enable both the receiver and the transmitter
251 * - Enable only the RX complete interrupt
253 #define SER_UART_BUS_TXINIT(_usart) do { \
254 USART_RX_ENABLE(_usart); \
255 USART_TX_ENABLE(_usart); \
256 USART_SET_RX_INTERRUPT_LEVEL(_usart, USART_RXCINTLVL_MED_gc); \
260 #ifndef SER_UART_BUS_TXBEGIN
262 * Invoked before starting a transmission
264 * - Enable both the receiver and the transmitter
265 * - Enable both the RX complete and UDR empty interrupts
267 #define SER_UART_BUS_TXBEGIN(_usart) do { \
268 USART_SET_RX_INTERRUPT_LEVEL(_usart, USART_RXCINTLVL_MED_gc); \
269 USART_SET_DRE_INTERRUPT_LEVEL(_usart, USART_DREINTLVL_MED_gc);\
273 #ifndef SER_UART_BUS_TXCHAR
275 * Invoked to send one character.
277 #define SER_UART_BUS_TXCHAR(_usart, c) do { \
278 USART_PUT_CHAR(_usart, c); \
282 #ifndef SER_UART_BUS_TXEND
284 * Invoked as soon as the txfifo becomes empty
286 * - Keep both the receiver and the transmitter enabled
287 * - Keep the RX complete interrupt enabled
288 * - Disable the UDR empty interrupt
290 #define SER_UART_BUS_TXEND(_usart) do { \
291 USART_SET_DRE_INTERRUPT_LEVEL(_usart, USART_DREINTLVL_OFF_gc); \
295 #ifndef SER_UART_BUS_TXOFF
297 * \def SER_UART_BUS_TXOFF
299 * Invoked after the last character has been transmitted
301 * The default is no action.
304 #define SER_UART_BUS_TXOFF(_usart)
310 /* From the high-level serial driver */
311 extern struct Serial *ser_handles[SER_CNT];
313 /* TX and RX buffers */
314 static unsigned char uart0_txbuffer[CONFIG_UART0_TXBUFSIZE];
315 static unsigned char uart0_rxbuffer[CONFIG_UART0_RXBUFSIZE];
316 static unsigned char uart1_txbuffer[CONFIG_UART1_TXBUFSIZE];
317 static unsigned char uart1_rxbuffer[CONFIG_UART1_RXBUFSIZE];
318 #ifdef CPU_AVR_XMEGA_A
319 static unsigned char uart2_txbuffer[CONFIG_UART2_TXBUFSIZE];
320 static unsigned char uart2_rxbuffer[CONFIG_UART2_RXBUFSIZE];
321 static unsigned char uart3_txbuffer[CONFIG_UART3_TXBUFSIZE];
322 static unsigned char uart3_rxbuffer[CONFIG_UART3_RXBUFSIZE];
323 static unsigned char uart4_txbuffer[CONFIG_UART4_TXBUFSIZE];
324 static unsigned char uart4_rxbuffer[CONFIG_UART4_RXBUFSIZE];
328 * Internal hardware state structure
330 * The \a sending variable is true while the transmission
331 * interrupt is retriggering itself.
333 * the \a usart variable will point to the USART_t structure
334 * that should be used.
336 * the \a port variable will point to the PORT_t structure
337 * that should be modified to set the tx pin as an output and the
340 * the \a txpin variable will hold the pinnumber of the pin to use
343 * the \a rxpin variable will hold the pinnumber of the pin to use
346 * For the USARTs the \a sending flag is useful for taking specific
347 * actions before sending a burst of data, at the start of a trasmission
348 * but not before every char sent.
350 * For the SPI, this flag is necessary because the SPI sends and receives
351 * bytes at the same time and the SPI IRQ is unique for send/receive.
352 * The only way to start transmission is to write data in SPDR (this
353 * is done by spi_starttx()). We do this *only* if a transfer is
354 * not already started.
356 struct AvrxmegaSerial
358 struct SerialHardware hw;
359 volatile bool sending;
360 volatile USART_t* usart;
361 volatile PORT_t* port;
368 * The same callbacks are used for all USARTS.
369 * By casting the SerialHardware structure to the AvrxmegaSerial
370 * structure a pointer to the USART_t structure can be obtained,
371 * to perform the callback for the specific USART.
372 * This methode might cost some more cpu time, but saves on
373 * code duplication and code size.
378 * \brief Initializes the uart
380 * The TX pin of the uart will be set as an outputpin
381 * The RX pin of the uart will be set as an inputpin
382 * The usart will be initialized
383 * \see SER_UART_BUS_TXINIT
385 * \param _hw struct AvrxmegaSerial
388 static void uart_init(struct SerialHardware * _hw, UNUSED_ARG(struct Serial *, ser))
390 struct AvrxmegaSerial *hw = (struct AvrxmegaSerial *)_hw;
391 //set transmit pin as output
392 hw->port->DIRSET = BV(hw->txpin);
393 hw->port->OUTCLR = BV(hw->txpin);
394 //set receive pin as input
395 hw->port->DIRCLR = BV(hw->rxpin);
396 //initialize the USART
397 SER_UART_BUS_TXINIT(hw->usart);
403 * \brief Cleans up / Disables the uart
405 * \param _hw struct AvrxmegaSerial
407 static void uart_cleanup(struct SerialHardware * _hw)
409 struct AvrxmegaSerial *hw = (struct AvrxmegaSerial *)_hw;
410 hw->usart->CTRLA = 0;
411 hw->usart->CTRLB = 0;
415 * \brief Enableds the TX interrupt
417 * \param _hw struct AvrxmegaSerial
419 static void uart_enabletxirq(struct SerialHardware *_hw)
421 struct AvrxmegaSerial *hw = (struct AvrxmegaSerial *)_hw;
424 * WARNING: racy code here! The tx interrupt sets hw->sending to false
425 * when it runs with an empty fifo. The order of statements in the
431 SER_UART_BUS_TXBEGIN(hw->usart);
436 * \brief sets the uart to the provided baudrate
438 * For setting the baudrate an scale factor (bscale) and a period
439 * setting (BSEL) is required.
441 * The scale factor should be privided by defining USART_SCALE_FACTOR
443 * Atmel specifies BSEL for normal speed mode and bscale >= 0 as:
444 * BSEL = (cpu_freq / ((2^bscale) * 16 * rate)) - 1
445 * To allow BSEL to be calculated with an power function this can be
447 * BSEL = BSEL = (cpu_freq / ((1 << bscale) * 16 * rate)) - 1
449 * Atmel specifies BSEL for normal speed mode and bscale < 0 as:
450 * BSEL = (1 / (2^bscale)) * ( (cpu_freq / (16 * rate)) - 1)
451 * To calculte this float atheritmic is required as the second product will be smaller
452 * than zero in a lot of cases.
453 * To allow BSEL to be calculated with interger devision and no power function
454 * this can be rewriten by folowing simple math rules to:
455 * BSEL = ((1 << -bscale) * (cpu_freq - (16 * rate)) / (16 * rate)
457 * \param _hw struct AvrxmegaSerial
458 * \param _rate the required baudrate
461 static void uart_setbaudrate(struct SerialHardware * _hw, unsigned long _rate)
463 struct AvrxmegaSerial *hw = (struct AvrxmegaSerial *)_hw;
464 /* Compute baud-rate period, this requires a valid USART_SCALE_FACTOR */
465 #if USART_SCALE_FACTOR < 0
466 uint16_t bsel = DIV_ROUND((1 << (-(USART_SCALE_FACTOR))) * (CPU_FREQ - (16 * _rate)), 16 * _rate);
468 uint16_t bsel = DIV_ROUND(CPU_FREQ, (1 << (USART_SCALE_FACTOR)) * 16 * _rate) - 1;
470 USART_SET_BAUDRATE(hw->usart, bsel, USART_SCALE_FACTOR);
474 * \brief Sets the parity of the uart
476 * \param _hw struct AvrxmegaSerial
477 * \param _parity the parity to set
479 static void uart_setparity(struct SerialHardware * _hw, int _parity)
481 struct AvrxmegaSerial *hw = (struct AvrxmegaSerial *)_hw;
482 USART_SET_MODE(hw->usart, _parity);
486 * \brief Returns true if Transmitter is sending
488 * \param _hw struct AvrxmegaSerial
489 * \return true if transmitter is sending
491 static bool tx_sending(struct SerialHardware* _hw)
493 struct AvrxmegaSerial *hw = (struct AvrxmegaSerial *)_hw;
498 // FIXME: move into compiler.h? Ditch?
500 #define C99INIT(name,val) .name = val
501 #elif defined(__GNUC__)
502 #define C99INIT(name,val) name: val
504 #warning No designated initializers, double check your code
505 #define C99INIT(name,val) (val)
509 * High-level interface data structures
511 static const struct SerialHardwareVT UART_VT =
513 C99INIT(init, uart_init),
514 C99INIT(cleanup, uart_cleanup),
515 C99INIT(setBaudrate, uart_setbaudrate),
516 C99INIT(setParity, uart_setparity),
517 C99INIT(txStart, uart_enabletxirq),
518 C99INIT(txSending, tx_sending)
521 static struct AvrxmegaSerial UARTDescs[SER_CNT] =
525 C99INIT(table, &UART_VT),
526 C99INIT(txbuffer, uart0_txbuffer),
527 C99INIT(rxbuffer, uart0_rxbuffer),
528 C99INIT(txbuffer_size, sizeof(uart0_txbuffer)),
529 C99INIT(rxbuffer_size, sizeof(uart0_rxbuffer)),
531 C99INIT(sending, false),
532 C99INIT(usart, &USARTC0),
533 C99INIT(port, &PORTC),
534 C99INIT(txpin, PIN3_bp),
535 C99INIT(rxpin, PIN2_bp),
539 C99INIT(table, &UART_VT),
540 C99INIT(txbuffer, uart1_txbuffer),
541 C99INIT(rxbuffer, uart1_rxbuffer),
542 C99INIT(txbuffer_size, sizeof(uart1_txbuffer)),
543 C99INIT(rxbuffer_size, sizeof(uart1_rxbuffer)),
545 C99INIT(sending, false),
546 C99INIT(usart, &USARTD0),
547 C99INIT(port, &PORTD),
548 C99INIT(txpin, PIN3_bp),
549 C99INIT(rxpin, PIN2_bp),
551 #ifdef CPU_AVR_XMEGA_A
554 C99INIT(table, &UART_VT),
555 C99INIT(txbuffer, uart2_txbuffer),
556 C99INIT(rxbuffer, uart2_rxbuffer),
557 C99INIT(txbuffer_size, sizeof(uart2_txbuffer)),
558 C99INIT(rxbuffer_size, sizeof(uart2_rxbuffer)),
560 C99INIT(sending, false),
561 C99INIT(usart, &USARTC1),
562 C99INIT(port, &PORTC),
563 C99INIT(txpin, PIN7_bp),
564 C99INIT(rxpin, PIN6_bp),
568 C99INIT(table, &UART_VT),
569 C99INIT(txbuffer, uart3_txbuffer),
570 C99INIT(rxbuffer, uart3_rxbuffer),
571 C99INIT(txbuffer_size, sizeof(uart3_txbuffer)),
572 C99INIT(rxbuffer_size, sizeof(uart3_rxbuffer)),
574 C99INIT(sending, false),
575 C99INIT(usart, &USARTD1),
576 C99INIT(port, &PORTD),
577 C99INIT(txpin, PIN7_bp),
578 C99INIT(rxpin, PIN6_bp),
582 C99INIT(table, &UART_VT),
583 C99INIT(txbuffer, uart4_txbuffer),
584 C99INIT(rxbuffer, uart4_rxbuffer),
585 C99INIT(txbuffer_size, sizeof(uart4_txbuffer)),
586 C99INIT(rxbuffer_size, sizeof(uart4_rxbuffer)),
588 C99INIT(sending, false),
589 C99INIT(usart, &USARTE0),
590 C99INIT(port, &PORTE),
591 C99INIT(txpin, PIN3_bp),
592 C99INIT(rxpin, PIN2_bp),
594 #endif //CPU_AVR_XMEGA_A
597 struct SerialHardware *ser_hw_getdesc(int unit)
599 ASSERT(unit < SER_CNT);
600 return &UARTDescs[unit].hw;
607 static inline void usart_handleDreInterrupt(uint8_t usartNumber)
610 struct FIFOBuffer * const txfifo = &ser_handles[usartNumber]->txfifo;
611 if (fifo_isempty(txfifo))
613 SER_UART_BUS_TXEND(UARTDescs[usartNumber].usart);
614 #ifndef SER_UART_BUS_TXOFF
615 UARTDescs[usartNumber].sending = false;
620 char c = fifo_pop(txfifo);
621 SER_UART_BUS_TXCHAR(UARTDescs[usartNumber].usart, c);
626 #define USART_DRE_INTERRUPT_VECTOR(_vector, _usart) \
627 DECLARE_ISR(_vector) \
629 usart_handleDreInterrupt( _usart ); \
632 USART_DRE_INTERRUPT_VECTOR(USARTC0_DRE_vect, SER_UART0)
633 USART_DRE_INTERRUPT_VECTOR(USARTD0_DRE_vect, SER_UART1)
634 #ifdef CPU_AVR_XMEGA_A
635 USART_DRE_INTERRUPT_VECTOR(USARTC1_DRE_vect, SER_UART2)
636 USART_DRE_INTERRUPT_VECTOR(USARTD1_DRE_VECT, SER_UART3)
637 USART_DRE_INTERRUPT_VECTOR(USARTE0_DRE_vect, SER_UART4)
640 #ifdef SER_UART_BUS_TXOFF
641 static inline void USART_handleTXCInterrupt(uint8_t usartNumber)
644 struct FIFOBuffer * const txfifo = &ser_handles[usartNumber]->txfifo;
645 if (fifo_isempty(txfifo))
647 SER_UART_BUS_TXOFF(UARTDescs[usartNumber].usart);
648 UARTDescs[usartNumber].sending = false;
652 SER_UART_BUS_TXBEGIN(UARTDescs[usartNumber].usart);
658 * Serial port 0 TX complete interrupt handler.
660 * This IRQ is usually disabled. The UDR-empty interrupt
661 * enables it when there's no more data to transmit.
662 * We need to wait until the last character has been
663 * transmitted before switching the 485 transceiver to
666 * The txfifo might have been refilled by putchar() while
667 * we were waiting for the transmission complete interrupt.
668 * In this case, we must restart the UDR empty interrupt,
669 * otherwise we'd stop the serial port with some data
670 * still pending in the buffer.
672 #define USART_TXC_INTERRUPT_VECTOR(_vector, _usart) \
673 DECLARE_ISR(_vector) \
675 USART_handleTXCInterrupt( _usart ); \
678 USART_TXC_INTERRUPT_VECTOR(USARTC0_TXC_vect, SER_UART0)
679 USART_TXC_INTERRUPT_VECTOR(USARTD0_TXC_vect, SER_UART1)
680 #ifdef CPU_AVR_XMEGA_A
681 USART_TXC_INTERRUPT_VECTOR(USARTC1_TXC_vect, SER_UART2)
682 USART_TXC_INTERRUPT_VECTOR(USARTD1_TXC_vect, SER_UART3)
683 USART_TXC_INTERRUPT_VECTOR(USARTE0_TXC_vect, SER_UART4)
684 #endif /* CPU_AVR_XMEGA_A */
685 #endif /* SER_UART_BUS_TXOFF */
688 * Serial RX complete interrupt handler.
690 * This handler is interruptible.
691 * Interrupt are reenabled as soon as recv complete interrupt is
692 * disabled. Using INTERRUPT() is troublesome when the serial
693 * is heavily loaded, because an interrupt could be retriggered
694 * when executing the handler prologue before RXCIE is disabled.
696 static inline void USART_handleRXCInterrupt(uint8_t usartNumber)
700 ser_handles[usartNumber]->status |= (UARTDescs[usartNumber].usart)->STATUS & (SERRF_RXSROVERRUN | SERRF_FRAMEERROR);
701 /* To clear the RXC flag we must _always_ read the UDR even when we're
702 * not going to accept the incoming data, otherwise a new interrupt
703 * will occur once the handler terminates.
705 char c = (UARTDescs[usartNumber].usart)->DATA;
706 struct FIFOBuffer * const rxfifo = &ser_handles[usartNumber]->rxfifo;
707 if (fifo_isfull(rxfifo))
709 ser_handles[usartNumber]->status |= SERRF_RXFIFOOVERRUN;
713 fifo_push(rxfifo, c);
714 #if CONFIG_SER_HWHANDSHAKE
715 if (fifo_isfull(rxfifo))
717 RTS_OFF(UARTDescs[usartNumber].usart);
724 #define USART_RXC_INTERRUPT_VECTOR(_vector, _usart) \
725 DECLARE_ISR(_vector) \
727 USART_handleRXCInterrupt( _usart ); \
729 USART_RXC_INTERRUPT_VECTOR(USARTC0_RXC_vect, SER_UART0)
730 USART_RXC_INTERRUPT_VECTOR(USARTD0_RXC_vect, SER_UART1)
731 #ifdef CPU_AVR_XMEGA_A
732 USART_RXC_INTERRUPT_VECTOR(USARTC1_RXC_vect, SER_UART2)
733 USART_RXC_INTERRUPT_VECTOR(USARTD1_RXC_vect, SER_UART3)
734 USART_RXC_INTERRUPT_VECTOR(USARTE0_RXC_vect, SER_UART4)