4 * This file is part of BeRTOS.
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20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
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29 * Copyright 2005 Develer S.r.l. (http://www.develer.com/)
35 * \author Bernie Innocenti <bernie@codewiz.org>
36 * \author Francesco Sacchi <batt@develer.com>
38 * \brief Low-level timer module for AVR (implementation).
40 * This module is automatically included so no need to include
45 #include <drv/timer_avr.h>
46 #include <cfg/macros.h> // BV()
48 #include <cpu/types.h>
51 #include <avr/interrupt.h>
54 #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA168
55 #define REG_TIFR0 TIFR0
56 #define REG_TIFR2 TIFR2
58 #define REG_TIMSK0 TIMSK0
59 #define REG_TIMSK2 TIMSK2
61 #define REG_TCCR0A TCCR0A
62 #define REG_TCCR0B TCCR0B
64 #define REG_TCCR2A TCCR2A
65 #define REG_TCCR2B TCCR2B
67 #define REG_OCR0A OCR0A
68 #define REG_OCR2A OCR2A
70 #define BIT_OCF0A OCF0A
71 #define BIT_OCF2A OCF2A
73 #define BIT_OCIE0A OCIE0A
74 #define BIT_OCIE2A OCIE2A
76 #define REG_TIFR0 TIFR
77 #define REG_TIFR2 TIFR
79 #define REG_TIMSK0 TIMSK
80 #define REG_TIMSK2 TIMSK
82 #define REG_TCCR0A TCCR0
83 #define REG_TCCR0B TCCR0
85 #define REG_TCCR2A TCCR2
86 #define REG_TCCR2B TCCR2
88 #define REG_OCR0A OCR0
89 #define REG_OCR2A OCR2
91 #define BIT_OCF0A OCF0
92 #define BIT_OCF2A OCF2
94 #define BIT_OCIE0A OCIE0
95 #define BIT_OCIE2A OCIE2
98 #if CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA103
99 /* These ATMega have different prescaler options. */
100 #define TIMER0_PRESCALER_64 BV(CS02)
101 #define TIMER2_PRESCALER_64 (BV(CS21) | BV(CS20))
103 #define TIMER0_PRESCALER_64 (BV(CS01) | BV(CS00))
104 #define TIMER2_PRESCALER_64 BV(CS22)
107 /** HW dependent timer initialization */
108 #if (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0)
110 static void timer_hw_init(void)
113 IRQ_SAVE_DISABLE(flags);
115 /* Reset Timer flags */
116 REG_TIFR0 = BV(BIT_OCF0A) | BV(TOV0);
118 /* Setup Timer/Counter interrupt */
119 ASSR = 0x00; /* Internal system clock */
121 REG_TCCR0A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to
124 REG_TCCR0A = BV(WGM01); /* Clear on Compare match */
125 #if TIMER_PRESCALER == 64
126 REG_TCCR0B |= TIMER0_PRESCALER_64;
128 #error Unsupported value of TIMER_PRESCALER
131 TCNT0 = 0x00; /* Initialization of Timer/Counter */
132 REG_OCR0A = OCR_DIVISOR; /* Timer/Counter Output Compare Register */
134 /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
135 REG_TIMSK0 &= ~BV(TOIE0);
136 REG_TIMSK0 |= BV(BIT_OCIE0A);
141 INLINE hptime_t timer_hw_hpread(void)
146 #elif (CONFIG_TIMER == TIMER_ON_OVERFLOW1)
148 static void timer_hw_init(void)
151 IRQ_SAVE_DISABLE(flags);
153 /* Reset Timer overflow flag */
154 REG_TIFR0 |= BV(TOV1);
156 /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */
157 #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9)
159 TCCR1A &= ~BV(WGM10);
160 TCCR1B |= BV(WGM12) | BV(CS10);
161 TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12));
162 /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */
163 #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8)
165 TCCR1A &= ~BV(WGM11);
166 TCCR1B |= BV(WGM12) | BV(CS10);
167 TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12));
169 #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS
172 TCNT1 = 0x00; /* initialization of Timer/Counter */
174 /* Enable timer interrupt: Timer/Counter1 Overflow */
175 REG_TIMSK0 |= BV(TOIE1);
180 INLINE hptime_t timer_hw_hpread(void)
185 #elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2)
186 static void timer_hw_init(void)
189 IRQ_SAVE_DISABLE(flags);
191 /* Reset Timer flags */
192 REG_TIFR2 = BV(BIT_OCF2A) | BV(TOV2);
194 /* Setup Timer/Counter interrupt */
195 REG_TCCR2A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to
196 REG_TCCR2B = 0; // ensure correct initialization.
198 REG_TCCR2A = BV(WGM21);
199 #if TIMER_PRESCALER == 64
200 REG_TCCR2B |= TIMER2_PRESCALER_64;
202 #error Unsupported value of TIMER_PRESCALER
205 /* Clear on Compare match & prescaler = 64, internal sys clock.
206 When changing prescaler change TIMER_HW_HPTICKS_PER_SEC too */
207 TCNT2 = 0x00; /* initialization of Timer/Counter */
208 REG_OCR2A = OCR_DIVISOR; /* Timer/Counter Output Compare Register */
210 /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
211 REG_TIMSK2 &= ~BV(TOIE2);
212 REG_TIMSK2 |= BV(BIT_OCIE2A);
217 INLINE hptime_t timer_hw_hpread(void)
221 #elif (CONFIG_TIMER == TIMER_ON_OVERFLOW3)
223 static void timer_hw_init(void)
226 IRQ_SAVE_DISABLE(flags);
228 /* Reset Timer overflow flag */
231 /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */
232 #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9)
234 TCCR3A &= ~BV(WGM30);
235 TCCR3B |= BV(WGM32) | BV(CS30);
236 TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32));
237 /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */
238 #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8)
240 TCCR3A &= ~BV(WGM31);
241 TCCR3B |= BV(WGM32) | BV(CS30);
242 TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32));
244 #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS
247 TCNT3 = 0x00; /* initialization of Timer/Counter */
249 /* Enable timer interrupt: Timer/Counter3 Overflow */
250 /* ATTENTION! TOIE3 is only on ETIMSK, not TIMSK */
256 INLINE hptime_t timer_hw_hpread(void)
262 #error Unimplemented value for CONFIG_TIMER
263 #endif /* CONFIG_TIMER */