4 * This file is part of BeRTOS.
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
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29 * Copyright 2005 Develer S.r.l. (http://www.develer.com/)
35 * \author Bernie Innocenti <bernie@codewiz.org>
36 * \author Francesco Sacchi <batt@develer.com>
38 * \brief Low-level timer module for AVR (implementation).
40 * This module is automatically included so no need to include
45 #include <drv/timer_avr.h>
46 #include <cfg/macros.h> // BV()
48 #include <cpu/types.h>
51 #include <avr/interrupt.h>
54 #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA168
55 #define REG_TIFR0 TIFR0
56 #define REG_TIFR1 TIFR1
57 #define REG_TIFR2 TIFR2
58 #if CPU_AVR_ATMEGA1281
59 #define REG_TIFR3 TIFR3
62 #define REG_TIMSK0 TIMSK0
63 #define REG_TIMSK1 TIMSK1
64 #define REG_TIMSK2 TIMSK2
65 #if CPU_AVR_ATMEGA1281
66 #define REG_TIMSK3 TIMSK3
69 #define REG_TCCR0A TCCR0A
70 #define REG_TCCR0B TCCR0B
72 #define REG_TCCR2A TCCR2A
73 #define REG_TCCR2B TCCR2B
75 #define REG_OCR0A OCR0A
76 #define REG_OCR2A OCR2A
78 #define BIT_OCF0A OCF0A
79 #define BIT_OCF2A OCF2A
81 #define BIT_OCIE0A OCIE0A
82 #define BIT_OCIE2A OCIE2A
84 #define REG_TIFR0 TIFR
85 #define REG_TIFR1 TIFR
86 #define REG_TIFR2 TIFR
88 #define REG_TIMSK0 TIMSK
89 #define REG_TIMSK1 TIMSK
90 #define REG_TIMSK2 TIMSK
91 #define REG_TIMSK3 ETIMSK
93 #define REG_TCCR0A TCCR0
94 #define REG_TCCR0B TCCR0
96 #define REG_TCCR2A TCCR2
97 #define REG_TCCR2B TCCR2
99 #define REG_OCR0A OCR0
100 #define REG_OCR2A OCR2
102 #define BIT_OCF0A OCF0
103 #define BIT_OCF2A OCF2
105 #define BIT_OCIE0A OCIE0
106 #define BIT_OCIE2A OCIE2
109 #if CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA103
110 /* These ATMega have different prescaler options. */
111 #define TIMER0_PRESCALER_64 BV(CS02)
112 #define TIMER2_PRESCALER_64 (BV(CS21) | BV(CS20))
114 #define TIMER0_PRESCALER_64 (BV(CS01) | BV(CS00))
115 #define TIMER2_PRESCALER_64 BV(CS22)
118 /** HW dependent timer initialization */
119 #if (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0)
121 static void timer_hw_init(void)
124 IRQ_SAVE_DISABLE(flags);
126 /* Reset Timer flags */
127 REG_TIFR0 = BV(BIT_OCF0A) | BV(TOV0);
129 /* Setup Timer/Counter interrupt */
130 ASSR = 0x00; /* Internal system clock */
132 REG_TCCR0A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to
135 REG_TCCR0A = BV(WGM01); /* Clear on Compare match */
136 #if TIMER_PRESCALER == 64
137 REG_TCCR0B |= TIMER0_PRESCALER_64;
139 #error Unsupported value of TIMER_PRESCALER
142 TCNT0 = 0x00; /* Initialization of Timer/Counter */
143 REG_OCR0A = OCR_DIVISOR; /* Timer/Counter Output Compare Register */
145 /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
146 REG_TIMSK0 &= ~BV(TOIE0);
147 REG_TIMSK0 |= BV(BIT_OCIE0A);
152 INLINE hptime_t timer_hw_hpread(void)
157 #elif (CONFIG_TIMER == TIMER_ON_OVERFLOW1)
159 static void timer_hw_init(void)
162 IRQ_SAVE_DISABLE(flags);
164 /* Reset Timer overflow flag */
165 REG_TIFR1 |= BV(TOV1);
167 /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */
168 #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9)
170 TCCR1A &= ~BV(WGM10);
171 TCCR1B |= BV(WGM12) | BV(CS10);
172 TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12));
173 /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */
174 #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8)
176 TCCR1A &= ~BV(WGM11);
177 TCCR1B |= BV(WGM12) | BV(CS10);
178 TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12));
180 #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS
183 TCNT1 = 0x00; /* initialization of Timer/Counter */
185 /* Enable timer interrupt: Timer/Counter1 Overflow */
186 REG_TIMSK1 |= BV(TOIE1);
191 INLINE hptime_t timer_hw_hpread(void)
196 #elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2)
197 static void timer_hw_init(void)
200 IRQ_SAVE_DISABLE(flags);
202 /* Reset Timer flags */
203 REG_TIFR2 = BV(BIT_OCF2A) | BV(TOV2);
205 /* Setup Timer/Counter interrupt */
206 REG_TCCR2A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to
207 REG_TCCR2B = 0; // ensure correct initialization.
209 REG_TCCR2A = BV(WGM21);
210 #if TIMER_PRESCALER == 64
211 REG_TCCR2B |= TIMER2_PRESCALER_64;
213 #error Unsupported value of TIMER_PRESCALER
216 /* Clear on Compare match & prescaler = 64, internal sys clock.
217 When changing prescaler change TIMER_HW_HPTICKS_PER_SEC too */
218 TCNT2 = 0x00; /* initialization of Timer/Counter */
219 REG_OCR2A = OCR_DIVISOR; /* Timer/Counter Output Compare Register */
221 /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
222 REG_TIMSK2 &= ~BV(TOIE2);
223 REG_TIMSK2 |= BV(BIT_OCIE2A);
228 INLINE hptime_t timer_hw_hpread(void)
232 #elif (CONFIG_TIMER == TIMER_ON_OVERFLOW3)
234 static void timer_hw_init(void)
237 IRQ_SAVE_DISABLE(flags);
239 /* Reset Timer overflow flag */
240 REG_TIFR3 |= BV(TOV3);
242 /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */
243 #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9)
245 TCCR3A &= ~BV(WGM30);
246 TCCR3B |= BV(WGM32) | BV(CS30);
247 TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32));
248 /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */
249 #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8)
251 TCCR3A &= ~BV(WGM31);
252 TCCR3B |= BV(WGM32) | BV(CS30);
253 TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32));
255 #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS
258 /* initialization of Timer/Counter */
261 /* Enable timer interrupt: Timer/Counter3 Overflow */
262 REG_TIMSK3 = |= BV(TOIE3);
267 INLINE hptime_t timer_hw_hpread(void)
273 #error Unimplemented value for CONFIG_TIMER
274 #endif /* CONFIG_TIMER */