4 * This file is part of BeRTOS.
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7 * it under the terms of the GNU General Public License as published by
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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21 * library without restriction. Specifically, if other files instantiate
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24 * file does not by itself cause the resulting executable to be covered by
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26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2005, 2010 Develer S.r.l. (http://www.develer.com/)
33 * \author Bernie Innocenti <bernie@codewiz.org>
34 * \author Francesco Sacchi <batt@develer.com>
35 * \author Luca Ottaviano <lottaviano@develer.com>
37 * \brief Low-level timer module for AVR (implementation).
39 * This module is automatically included so no need to include
44 #include <drv/timer_avr.h>
45 #include <cfg/macros.h> // BV()
47 #include <cpu/types.h>
52 #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
53 #define REG_TIFR0 TIFR0
54 #define REG_TIFR1 TIFR1
55 #define REG_TIFR2 TIFR2
56 #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280
57 #define REG_TIFR3 TIFR3
60 #define REG_TIMSK0 TIMSK0
61 #define REG_TIMSK1 TIMSK1
62 #define REG_TIMSK2 TIMSK2
63 #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280
64 #define REG_TIMSK3 TIMSK3
67 #define REG_TCCR0A TCCR0A
68 #define REG_TCCR0B TCCR0B
70 #define REG_TCCR2A TCCR2A
71 #define REG_TCCR2B TCCR2B
73 #define REG_OCR0A OCR0A
74 #define REG_OCR2A OCR2A
76 #define BIT_OCF0A OCF0A
77 #define BIT_OCF2A OCF2A
79 #define BIT_OCIE0A OCIE0A
80 #define BIT_OCIE2A OCIE2A
82 #define REG_TIFR0 TIFR
83 #define REG_TIFR1 TIFR
84 #define REG_TIFR2 TIFR
85 #define REG_TIFR3 TIFR
87 #define REG_TIMSK0 TIMSK
88 #define REG_TIMSK1 TIMSK
89 #define REG_TIMSK2 TIMSK
90 #define REG_TIMSK3 ETIMSK
92 #define REG_TCCR0A TCCR0
93 #define REG_TCCR0B TCCR0
95 #define REG_TCCR2A TCCR2
96 #define REG_TCCR2B TCCR2
98 #define REG_OCR0A OCR0
99 #define REG_OCR2A OCR2
101 #define BIT_OCF0A OCF0
102 #define BIT_OCF2A OCF2
104 #define BIT_OCIE0A OCIE0
105 #define BIT_OCIE2A OCIE2
108 #if CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA103
109 /* These ATMega have different prescaler options. */
110 #define TIMER0_PRESCALER_64 BV(CS02)
111 #define TIMER2_PRESCALER_64 (BV(CS21) | BV(CS20))
113 #define TIMER0_PRESCALER_64 (BV(CS01) | BV(CS00))
114 #define TIMER2_PRESCALER_64 BV(CS22)
117 /** HW dependent timer initialization */
118 #if (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0)
120 void timer_hw_init(void)
123 IRQ_SAVE_DISABLE(flags);
125 /* Reset Timer flags */
126 REG_TIFR0 = BV(BIT_OCF0A) | BV(TOV0);
128 /* Setup Timer/Counter interrupt */
129 ASSR = 0x00; /* Internal system clock */
131 REG_TCCR0A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to
134 REG_TCCR0A = BV(WGM01); /* Clear on Compare match */
135 #if TIMER_PRESCALER == 64
136 REG_TCCR0B |= TIMER0_PRESCALER_64;
138 #error Unsupported value of TIMER_PRESCALER
141 TCNT0 = 0x00; /* Initialization of Timer/Counter */
142 REG_OCR0A = OCR_DIVISOR; /* Timer/Counter Output Compare Register */
144 /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
145 REG_TIMSK0 &= ~BV(TOIE0);
146 REG_TIMSK0 |= BV(BIT_OCIE0A);
151 #elif (CONFIG_TIMER == TIMER_ON_OVERFLOW1)
153 void timer_hw_init(void)
156 IRQ_SAVE_DISABLE(flags);
158 /* Reset Timer overflow flag */
159 REG_TIFR1 |= BV(TOV1);
161 /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */
162 #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9)
164 TCCR1A &= ~BV(WGM10);
165 TCCR1B |= BV(WGM12) | BV(CS10);
166 TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12));
167 /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */
168 #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8)
170 TCCR1A &= ~BV(WGM11);
171 TCCR1B |= BV(WGM12) | BV(CS10);
172 TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12));
174 #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS
177 TCNT1 = 0x00; /* initialization of Timer/Counter */
179 /* Enable timer interrupt: Timer/Counter1 Overflow */
180 REG_TIMSK1 |= BV(TOIE1);
185 #elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2)
186 void timer_hw_init(void)
189 IRQ_SAVE_DISABLE(flags);
191 /* Reset Timer flags */
192 REG_TIFR2 = BV(BIT_OCF2A) | BV(TOV2);
194 /* Setup Timer/Counter interrupt */
195 REG_TCCR2A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to
196 REG_TCCR2B = 0; // ensure correct initialization.
198 REG_TCCR2A = BV(WGM21);
199 #if TIMER_PRESCALER == 64
200 REG_TCCR2B |= TIMER2_PRESCALER_64;
202 #error Unsupported value of TIMER_PRESCALER
205 /* Clear on Compare match & prescaler = 64, internal sys clock.
206 When changing prescaler change TIMER_HW_HPTICKS_PER_SEC too */
207 TCNT2 = 0x00; /* initialization of Timer/Counter */
208 REG_OCR2A = (uint8_t)OCR_DIVISOR; /* Timer/Counter Output Compare Register */
210 /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
211 REG_TIMSK2 &= ~BV(TOIE2);
212 REG_TIMSK2 |= BV(BIT_OCIE2A);
217 #elif (CONFIG_TIMER == TIMER_ON_OVERFLOW3)
219 #if CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P || CPU_AVR_ATMEGA32
220 #error For select target there is not TIMER_ON_OVERFLOW3, please select an other one.
223 void timer_hw_init(void)
226 IRQ_SAVE_DISABLE(flags);
228 /* Reset Timer overflow flag */
229 REG_TIFR3 |= BV(TOV3);
231 /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */
232 #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9)
234 TCCR3A &= ~BV(WGM30);
235 TCCR3B |= BV(WGM32) | BV(CS30);
236 TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32));
237 /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */
238 #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8)
240 TCCR3A &= ~BV(WGM31);
241 TCCR3B |= BV(WGM32) | BV(CS30);
242 TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32));
244 #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS
247 /* initialization of Timer/Counter */
250 /* Enable timer interrupt: Timer/Counter3 Overflow */
251 REG_TIMSK3 |= BV(TOIE3);
257 #error Unimplemented value for CONFIG_TIMER
258 #endif /* CONFIG_TIMER */