4 * This file is part of BeRTOS.
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13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
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18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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21 * library without restriction. Specifically, if other files instantiate
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29 * Copyright 2005, 2010 Develer S.r.l. (http://www.develer.com/)
33 * \author Bernie Innocenti <bernie@codewiz.org>
34 * \author Francesco Sacchi <batt@develer.com>
35 * \author Luca Ottaviano <lottaviano@develer.com>
37 * \brief Low-level timer module for AVR (implementation).
39 * This module is automatically included so no need to include
44 #include <drv/timer_avr.h>
45 #include <cfg/macros.h> // BV()
47 #include <cpu/types.h>
52 #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
53 #define REG_TIFR0 TIFR0
54 #define REG_TIFR1 TIFR1
55 #define REG_TIFR2 TIFR2
56 #if CPU_AVR_ATMEGA1281
57 #define REG_TIFR3 TIFR3
60 #define REG_TIMSK0 TIMSK0
61 #define REG_TIMSK1 TIMSK1
62 #define REG_TIMSK2 TIMSK2
63 #if CPU_AVR_ATMEGA1281
64 #define REG_TIMSK3 TIMSK3
67 #define REG_TCCR0A TCCR0A
68 #define REG_TCCR0B TCCR0B
70 #define REG_TCCR2A TCCR2A
71 #define REG_TCCR2B TCCR2B
73 #define REG_OCR0A OCR0A
74 #define REG_OCR2A OCR2A
76 #define BIT_OCF0A OCF0A
77 #define BIT_OCF2A OCF2A
79 #define BIT_OCIE0A OCIE0A
80 #define BIT_OCIE2A OCIE2A
82 #define REG_TIFR0 TIFR
83 #define REG_TIFR1 TIFR
84 #define REG_TIFR2 TIFR
86 #define REG_TIMSK0 TIMSK
87 #define REG_TIMSK1 TIMSK
88 #define REG_TIMSK2 TIMSK
89 #define REG_TIMSK3 ETIMSK
91 #define REG_TCCR0A TCCR0
92 #define REG_TCCR0B TCCR0
94 #define REG_TCCR2A TCCR2
95 #define REG_TCCR2B TCCR2
97 #define REG_OCR0A OCR0
98 #define REG_OCR2A OCR2
100 #define BIT_OCF0A OCF0
101 #define BIT_OCF2A OCF2
103 #define BIT_OCIE0A OCIE0
104 #define BIT_OCIE2A OCIE2
107 #if CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA103
108 /* These ATMega have different prescaler options. */
109 #define TIMER0_PRESCALER_64 BV(CS02)
110 #define TIMER2_PRESCALER_64 (BV(CS21) | BV(CS20))
112 #define TIMER0_PRESCALER_64 (BV(CS01) | BV(CS00))
113 #define TIMER2_PRESCALER_64 BV(CS22)
116 /** HW dependent timer initialization */
117 #if (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0)
119 void timer_hw_init(void)
122 IRQ_SAVE_DISABLE(flags);
124 /* Reset Timer flags */
125 REG_TIFR0 = BV(BIT_OCF0A) | BV(TOV0);
127 /* Setup Timer/Counter interrupt */
128 ASSR = 0x00; /* Internal system clock */
130 REG_TCCR0A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to
133 REG_TCCR0A = BV(WGM01); /* Clear on Compare match */
134 #if TIMER_PRESCALER == 64
135 REG_TCCR0B |= TIMER0_PRESCALER_64;
137 #error Unsupported value of TIMER_PRESCALER
140 TCNT0 = 0x00; /* Initialization of Timer/Counter */
141 REG_OCR0A = OCR_DIVISOR; /* Timer/Counter Output Compare Register */
143 /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
144 REG_TIMSK0 &= ~BV(TOIE0);
145 REG_TIMSK0 |= BV(BIT_OCIE0A);
150 #elif (CONFIG_TIMER == TIMER_ON_OVERFLOW1)
152 void timer_hw_init(void)
155 IRQ_SAVE_DISABLE(flags);
157 /* Reset Timer overflow flag */
158 REG_TIFR1 |= BV(TOV1);
160 /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */
161 #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9)
163 TCCR1A &= ~BV(WGM10);
164 TCCR1B |= BV(WGM12) | BV(CS10);
165 TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12));
166 /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */
167 #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8)
169 TCCR1A &= ~BV(WGM11);
170 TCCR1B |= BV(WGM12) | BV(CS10);
171 TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12));
173 #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS
176 TCNT1 = 0x00; /* initialization of Timer/Counter */
178 /* Enable timer interrupt: Timer/Counter1 Overflow */
179 REG_TIMSK1 |= BV(TOIE1);
184 #elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2)
185 void timer_hw_init(void)
188 IRQ_SAVE_DISABLE(flags);
190 /* Reset Timer flags */
191 REG_TIFR2 = BV(BIT_OCF2A) | BV(TOV2);
193 /* Setup Timer/Counter interrupt */
194 REG_TCCR2A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to
195 REG_TCCR2B = 0; // ensure correct initialization.
197 REG_TCCR2A = BV(WGM21);
198 #if TIMER_PRESCALER == 64
199 REG_TCCR2B |= TIMER2_PRESCALER_64;
201 #error Unsupported value of TIMER_PRESCALER
204 /* Clear on Compare match & prescaler = 64, internal sys clock.
205 When changing prescaler change TIMER_HW_HPTICKS_PER_SEC too */
206 TCNT2 = 0x00; /* initialization of Timer/Counter */
207 REG_OCR2A = (uint8_t)OCR_DIVISOR; /* Timer/Counter Output Compare Register */
209 /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
210 REG_TIMSK2 &= ~BV(TOIE2);
211 REG_TIMSK2 |= BV(BIT_OCIE2A);
216 #elif (CONFIG_TIMER == TIMER_ON_OVERFLOW3)
218 void timer_hw_init(void)
221 IRQ_SAVE_DISABLE(flags);
223 /* Reset Timer overflow flag */
224 REG_TIFR3 |= BV(TOV3);
226 /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */
227 #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9)
229 TCCR3A &= ~BV(WGM30);
230 TCCR3B |= BV(WGM32) | BV(CS30);
231 TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32));
232 /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */
233 #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8)
235 TCCR3A &= ~BV(WGM31);
236 TCCR3B |= BV(WGM32) | BV(CS30);
237 TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32));
239 #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS
242 /* initialization of Timer/Counter */
245 /* Enable timer interrupt: Timer/Counter3 Overflow */
246 REG_TIMSK3 = |= BV(TOIE3);
252 #error Unimplemented value for CONFIG_TIMER
253 #endif /* CONFIG_TIMER */