4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2005 Develer S.r.l. (http://www.develer.com/)
35 * \author Bernie Innocenti <bernie@codewiz.org>
36 * \author Francesco Sacchi <batt@develer.com>
38 * \brief Low-level timer module for AVR (implementation).
40 * This module is automatically included so no need to include
45 #include <drv/timer_avr.h>
46 #include <cfg/macros.h> // BV()
48 #include <cpu/types.h>
51 #include <avr/interrupt.h>
54 #if CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA168
55 #define REG_TIFR0 TIFR0
56 #define REG_TIFR2 TIFR2
58 #define REG_TIMSK0 TIMSK0
59 #define REG_TIMSK2 TIMSK2
61 #define REG_TCCR2A TCCR2A
62 #define REG_TCCR2B TCCR2B
64 #define REG_OCR2A OCR2A
66 #define BIT_OCF0A OCF0A
67 #define BIT_OCF2A OCF2A
69 #define BIT_OCIE0A OCIE0A
70 #define BIT_OCIE2A OCIE2A
72 #define REG_TIFR0 TIFR
73 #define REG_TIFR2 TIFR
75 #define REG_TIMSK0 TIMSK
76 #define REG_TIMSK2 TIMSK
78 #define REG_TCCR2A TCCR2
79 #define REG_TCCR2B TCCR2
81 #define REG_OCR2A OCR2
83 #define BIT_OCF0A OCF0
84 #define BIT_OCF2A OCF2
86 #define BIT_OCIE0A OCIE0
87 #define BIT_OCIE2A OCIE2
90 #if CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA103
91 /* These ATMega have different prescaler options. */
92 #define TIMER0_PRESCALER_64 BV(CS02)
93 #define TIMER2_PRESCALER_64 (BV(CS21) | BV(CS20))
95 #define TIMER0_PRESCALER_64 (BV(CS01) | BV(CS00))
96 #define TIMER2_PRESCALER_64 BV(CS22)
99 /** HW dependent timer initialization */
100 #if (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE0)
102 static void timer_hw_init(void)
105 IRQ_SAVE_DISABLE(flags);
107 /* Reset Timer flags */
108 REG_TIFR0 = BV(BIT_OCF0A) | BV(TOV0);
110 /* Setup Timer/Counter interrupt */
111 ASSR = 0x00; /* Internal system clock */
112 TCCR0 = BV(WGM01) /* Clear on Compare match */
113 #if TIMER_PRESCALER == 64
114 | TIMER0_PRESCALER_64
116 #error Unsupported value of TIMER_PRESCALER
119 TCNT0 = 0x00; /* Initialization of Timer/Counter */
120 OCR0 = OCR_DIVISOR; /* Timer/Counter Output Compare Register */
122 /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
123 REG_TIMSK0 &= ~BV(TOIE0);
124 REG_TIMSK0 |= BV(OCIE0);
129 INLINE hptime_t timer_hw_hpread(void)
134 #elif (CONFIG_TIMER == TIMER_ON_OVERFLOW1)
136 static void timer_hw_init(void)
139 IRQ_SAVE_DISABLE(flags);
141 /* Reset Timer overflow flag */
144 /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */
145 #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9)
147 TCCR1A &= ~BV(WGM10);
148 TCCR1B |= BV(WGM12) | BV(CS10);
149 TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12));
150 /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */
151 #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8)
153 TCCR1A &= ~BV(WGM11);
154 TCCR1B |= BV(WGM12) | BV(CS10);
155 TCCR1B &= ~(BV(WGM13) | BV(CS11) | BV(CS12));
157 #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS
160 TCNT1 = 0x00; /* initialization of Timer/Counter */
162 /* Enable timer interrupt: Timer/Counter1 Overflow */
168 INLINE hptime_t timer_hw_hpread(void)
173 #elif (CONFIG_TIMER == TIMER_ON_OUTPUT_COMPARE2)
174 static void timer_hw_init(void)
177 IRQ_SAVE_DISABLE(flags);
179 /* Reset Timer flags */
180 REG_TIFR2 = BV(BIT_OCF2A) | BV(TOV2);
182 /* Setup Timer/Counter interrupt */
183 REG_TCCR2A = 0; // TCCR2 reg could be separate or a unique register with both A & B values, this is needed to
184 REG_TCCR2B = 0; // ensure correct initialization.
186 REG_TCCR2A = BV(WGM21);
187 #if TIMER_PRESCALER == 64
188 REG_TCCR2B |= TIMER2_PRESCALER_64;
190 #error Unsupported value of TIMER_PRESCALER
193 /* Clear on Compare match & prescaler = 64, internal sys clock.
194 When changing prescaler change TIMER_HW_HPTICKS_PER_SEC too */
195 TCNT2 = 0x00; /* initialization of Timer/Counter */
196 REG_OCR2A = OCR_DIVISOR; /* Timer/Counter Output Compare Register */
198 /* Enable timer interrupts: Timer/Counter2 Output Compare (OCIE2) */
199 REG_TIMSK2 &= ~BV(TOIE2);
200 REG_TIMSK2 |= BV(BIT_OCIE2A);
205 INLINE hptime_t timer_hw_hpread(void)
209 #elif (CONFIG_TIMER == TIMER_ON_OVERFLOW3)
211 static void timer_hw_init(void)
214 IRQ_SAVE_DISABLE(flags);
216 /* Reset Timer overflow flag */
219 /* Fast PWM mode, 9 bit, 24 kHz, no prescaling. */
220 #if (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 9)
222 TCCR3A &= ~BV(WGM30);
223 TCCR3B |= BV(WGM32) | BV(CS30);
224 TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32));
225 /* Fast PWM mode, 8 bit, 24 kHz, no prescaling. */
226 #elif (TIMER_PRESCALER == 1) && (TIMER_HW_BITS == 8)
228 TCCR3A &= ~BV(WGM31);
229 TCCR3B |= BV(WGM32) | BV(CS30);
230 TCCR3B &= ~(BV(WGM33) | BV(CS31) | BV(CS32));
232 #error Unsupported value of TIMER_PRESCALER or TIMER_HW_BITS
235 TCNT3 = 0x00; /* initialization of Timer/Counter */
237 /* Enable timer interrupt: Timer/Counter3 Overflow */
238 /* ATTENTION! TOIE3 is only on ETIMSK, not TIMSK */
244 INLINE hptime_t timer_hw_hpread(void)
250 #error Unimplemented value for CONFIG_TIMER
251 #endif /* CONFIG_TIMER */