4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
23 * this file and link it with other files to produce an executable, this
24 * file does not by itself cause the resulting executable to be covered by
25 * the GNU General Public License. This exception does not however
26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2011 Develer S.r.l. (http://www.develer.com/)
33 * \brief ADC hardware-specific implementation
35 * \author Daniele Basile <asterix@develer.com>
41 #include "cfg/cfg_adc.h"
43 #include <cfg/macros.h>
44 #include <cfg/compiler.h>
46 // Define log settings for cfg/log.h.
47 #define LOG_LEVEL ADC_LOG_LEVEL
48 #define LOG_FORMAT ADC_LOG_FORMAT
52 #include <drv/irq_cm3.h>
56 #include <mware/event.h>
61 static Event data_ready;
67 static DECLARE_ISR(adc_conversion_end_irq)
70 if (ADC_ISR & BV(ADC_DRDY))
73 event_do(&data_ready);
78 * Select mux channel \a ch.
80 void adc_hw_select_ch(uint8_t ch)
82 /* Disable all channels */
83 ADC_CHDR = ADC_CH_MASK;
84 /* Enable select channel */
90 * Start an ADC convertion.
92 uint16_t adc_hw_read(void)
94 ADC_CR = BV(ADC_START);
95 event_wait(&data_ready);
102 void adc_hw_init(void)
104 /* Make sure that interrupt are enabled */
105 IRQ_ASSERT_ENABLED();
107 /* Initialize the dataready event */
108 event_initGeneric(&data_ready);
110 /* Clock ADC peripheral */
111 pmc_periphEnable(ADC_ID);
114 /* Reset adc controller */
118 * Set adc mode register:
119 * - Disable hardware trigger and enable software trigger.
120 * - Select normal mode.
124 /* Set ADC_BITS bit convertion resolution. */
126 ADC_MR &= ~BV(ADC_LOWRES);
128 ADC_MR |= BV(ADC_LOWRES);
130 #error No select bit resolution is supported to this CPU
134 LOG_INFO("Computed ADC_CLOCK %ld\n", ADC_CLOCK);
135 ADC_MR |= ((ADC_PRESCALER << ADC_PRESCALER_SHIFT) & ADC_PRESCALER_MASK);
136 LOG_INFO("prescaler[%ld]\n", ADC_PRESCALER);
137 ADC_MR |= ((ADC_SUT512 << ADC_STARTUP_SHIFT) & ADC_STARTUP_MASK);
138 LOG_INFO("starup[%d]\n", ADC_SUT512);
139 ADC_MR |= ((ADC_AST17 << ADC_SETTLING_SHIFT) & ADC_SETTLING_MASK);
140 LOG_INFO("sttime[%d]\n", ADC_AST17);
141 ADC_MR |= ((0 << ADC_TRACKTIM_SHIFT) & ADC_TRACKTIM_MASK);
142 LOG_INFO("tracking[%d]\n", 0);
143 ADC_MR |= ((1 << ADC_TRANSFER_SHIFT) & ADC_TRANSFER_MASK);
144 LOG_INFO("tranfer[%d]\n", 1);
146 /* Register and enable irq for adc. */
147 sysirq_setHandler(INT_ADC, adc_conversion_end_irq);
148 ADC_IER = BV(ADC_DRDY);