4 * This file is part of BeRTOS.
6 * Bertos is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
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12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 * As a special exception, you may use this file as part of a free software
21 * library without restriction. Specifically, if other files instantiate
22 * templates or use macros or inline functions from this file, or you compile
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24 * file does not by itself cause the resulting executable to be covered by
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26 * invalidate any other reasons why the executable file might be covered by
27 * the GNU General Public License.
29 * Copyright 2008 Develer S.r.l. (http://www.develer.com/)
33 * \brief ADC hardware-specific implementation
35 * This ADC module should be use both whit kernel or none.
36 * If you are using a kernel, the adc drive does not wait the finish of
37 * conversion but use a singal every time a required conversion are
38 * ended. This signal wake up a process that return a result of
39 * conversion. Otherwise, if you not use a kernl, this module wait
40 * whit a loop the finishing of conversion.
43 * \author Daniele Basile <asterix@develer.com>
47 #include "adc_stm32.h"
51 #include "cfg/cfg_adc.h"
52 #include "cfg/cfg_proc.h"
53 #include "cfg/cfg_signal.h"
55 #include <cfg/macros.h>
56 #include <cfg/compiler.h>
57 #include <cfg/debug.h>
59 // Define log settings for cfg/log.h.
60 #define LOG_LEVEL ADC_LOG_LEVEL
61 #define LOG_FORMAT ADC_LOG_FORMAT
65 #include <drv/clock_stm32.h>
66 #include <drv/gpio_stm32.h>
67 #include <drv/irq_cm3.h>
72 struct stm32_adc *adc = (struct stm32_adc *)ADC1_BASE;
75 * Select mux channel \a ch.
77 void adc_hw_select_ch(uint8_t ch)
79 kprintf("Select[%d]\n", ch);
80 adc->SQR1 |= (0x1 << SQR1_SQ_LEN_SHIFT);
81 adc->SQR3 = (ch & SQR3_SQ_MASK);
84 static DECLARE_ISR(adc_redyRead)
89 * Start an ADC convertion.
90 * If a kernel is present, preempt until convertion is complete, otherwise
91 * a busy wait on ADC_DRDY bit is done.
93 uint16_t adc_hw_read(void)
96 adc->CR2 |= CR2_EXTTRIG_SWSTRT_SET;
98 while (!(adc->SR & BV(SR_EOC)));
100 //Return the last converted data
107 void adc_hw_init(void)
109 /* Enable clocking on AFIO */
110 RCC->APB2ENR |= RCC_APB2_AFIO;
111 RCC->APB2ENR |= RCC_APB2_GPIOC;
112 RCC->APB2ENR |= RCC_APB2_ADC1;
114 /* Reset cr1 registry */
123 adc->CR2 |= (BV(CR2_ADON) | ADC_EXTERNALTRIGCONV_NONE | BV(CR2_TSVREFE));
125 * Configure ADC settings
133 /* Set 17.1usec sampling time on channel 16 and 17 */
134 adc->SMPR1 |= ((ADC_SAMPLETIME_239CYCLES5 << ADC_CHANNEL_16) |
135 (ADC_SAMPLETIME_239CYCLES5 << ADC_CHANNEL_17));
137 /* Register the IRQ handler */
138 sysirq_setHandler(ADC_IRQHANDLER, adc_redyRead);
139 //adc->CR1 |= BV(CR1_EOCIE);